Yamaha RX-V2500 Service Manual page 80

Av receiver, av amplifier
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A
B
C
RX-V2500/DSP-AX2500
SCHEMATIC DIAGRAM (CONTROL 1/2)
1
Page 72
B1
to DSP_CB505_19Pin
ANALOG IN
5.0
5.0
5.0
2
FRONT L
CENTER
SURROUND BACK L
PRESENCE L
3
4.9
4
3.0
5.1
5.0
5.0
5.0
5.1
0
5.0
5
5.1
5.1
5.1
0.1
5.1
0.1
5.1
5.1
5.1
5.1
0.1
0
0
0.1
5.1
0
2.1
5.1
5.0
0
0.1
0
1.1
5.1
1.7
5.1
0.1
2.0
0.1
1.4
1.6
0.1
1.4
5.1
0
5.1
5.1
5.1
6
0.1
0
5.1
2.1
2.1
5.1
5.1
1.1
5.1
5.1
5.1
0.1
1.7
0
5.1
5.1
5.1
0.1
1.8
5.1
5.1
5.1
0.1
1.4
5.1
1.7
5.1
0
5.1
5.1
1.2
0
0
5.1
0
0.1
1.5
0
0
0
0.1
1.4
0.1
0.1
2.1
1.6
0.1
0
1.1
1.4
5.0
0
1.7
2.0
4.9
2.0
1.7
0
1.4
1.1
5.1
5.1
1.6
1.5
0
5.1
1.4
2.1
0
0
5.1
5.1
5.1
0
1.2
5.0
7
1.7
5.0
1.4
0.1
1.8
0
1.7
5.0
1.1
0
2.1
0
2.1
0
5.1
5.1
1
2
C-1
8
Key Input (A-D) Pull-Up Resistance 10 k-ohms
U, C, A models
O
0
+ 1.2k
+ 1.2k
+ 1.8k
+ 2.7k
+ 3.3k
+ 4.7k
V
~ 0.27
~ 0.75
~ 1.22
~ 1.76
~ 2.28
~ 2.76
~ 3.24
PRESET/TUNING
PRESET/TUNING
PRESET/TUNING
TUNING
KEY0
FM/AM
MEMORY
9
<
>
EDIT
MODE
SPEAKERS
SPEAKERS
PURE
TONE
STRAIGHT
KEY1
INPUT MODE
A/B/C/D/E
A
B
DIRECT
CONTROL
EFFECT
R, T, K, L, J models
O
0
+ 1.2k
+ 1.2k
+ 1.8k
+ 2.7k
+ 3.3k
+ 4.7k
V
~ 0.27
~ 0.75
~ 1.22
~ 1.76
~ 2.28
~ 2.76
~ 3.24
PRESET/TUNING
PRESET/TUNING
PRESET/TUNING
TUNING
KEY0
FM/AM
MEMORY
<
>
EDIT
MODE
SPEAKERS
SPEAKERS
PURE
TONE
STRAIGHT
KEY1
INPUT MODE
A/B/C/D/E
A
B
DIRECT
CONTROL
EFFECT
B, G models
O
0
+ 1.2k
+ 1.2k
+ 1.8k
+ 2.7k
+ 3.3k
+ 4.7k
V
~ 0.27
~ 0.75
~ 1.22
~ 1.76
~ 2.28
~ 2.76
~ 3.24
PRESET/TUNING
PRESET/TUNING
PRESET/TUNING
TUNING
RDS
KEY0
FM/AM
MEMORY
<
>
EDIT
MODE
MODE
SPEAKERS
SPEAKERS
PURE
TONE
STRAIGHT
KEY1
INPUT MODE
A/B/C/D/E
A
B
DIRECT
CONTROL
EFFECT
10
80
D
E
F
RGB ENCODER
4.9
2.5
2.5
2.5
1.6
4.0
4.9
1.5
2.5
2.5
2.5
0
0
0
3.2
3.2
0.1
0.1
3.2
3.2
3.2
0.1
0.1
3.2
3.2
3.2
0
0
3.2
3.2
0
3.2
0
3.2
3.2
3.2
0
3.2
5.1
5.1
1.5
0
5.1
2.1
5.0
16 bit µ-COM MAIN CPU
1.1
4.0
5.1
2.1
0
5.1
5.1
1.5
1.5
5.1
1.1
0.1
0.5
1.0
3.7
1.7
0
3.0
0.1
0.1
0.5
0
3.0
0.1
0.1
0.5
0
3.0
0.1
POINT B-1 Pin 20 of IC501
5.0
5.0
0.1
0.3
5.1
4.9
5.0
5.0
4.4
2.0
1.4
0.1
0
0.1
1.6
5.0
0
1.4
5.0
0.1
0
5.0
0
5.0
5.0
0.1
5.0
0.1
0
0.1
0
4.8
5.0
5.0
5.0
0.1
0.2
0.1
3.0
5.0
3.0
4.8
3.0
3.9
1.5
5.1
0.1
0.1
0
0
0.1
5.0
5.1
5.0
B-1
5.0
5.0
0.1
0
0
0
0
5.0
0
0
0.1
5.1
0.1
3.1
3.6
0
0
5.0
8.6
5.9
5.1
3.9
0
5.1
9.3
3.9
0
5.1
4.4
3.7
4.4
Page 71
to DSP_CB503_23Pin
+ 8.2k
+ 18.0k
+ 47.0k
~ 3.76
~ 4.26
~ 4.75
ZONE ON/OFF
ZONE ON/OFF
MAIN
ZONE2
+ 8.2k
+ 18.0k
+ 47.0k
~ 3.76
~ 4.26
~ 4.75
IC556, 558: SN74LV32APWR
Quadruple 2-Input Positive-OR Gates
+ 8.2k
+ 18.0k
+ 47.0k
~ 3.76
~ 4.26
~ 4.75
1A
1
14
Vcc
PTY
PTY
EON
MODE
START
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
G
H
3.0
0
3.0
0
0
0
0
B-2
0
2.2
0
1.9
3.0
0
0
3.1
0
1.5
2.2
3.2
0
2.5
2.2
3.0
2.2
0.1
0.1
0
2.1
0.1
0.1
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0
3.0
POINT B-2 Pin 239 of IC502
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
0.1
0
0
0
0.1
0
0.1
0
0.1
5.1
0.1
3.0
0.1
3.2
0
3.2
0.1
0.1
0
0.1
0
0.1
3.0
1.4
0
0.1
1.7
0.1
0
0.9
3.0
0.1
0.1
0.1
2.6
0.1
3.0
2.8
0
0
2.6
2.2
3.0
2.8
11.2
11.2
11.2
-11.9
0.1
0
11.2
11.2
11.2
-11.9
0.1
0
5.1
0
11.2
5.1
11.2
11.2
-11.9
0.1
0
11.2
11.2
11.2
-11.9
0.1
0
11.2
5.1
11.2
5.1
4.4
5.1
11.2
5.1
-11.9
0.1
0.1
0.1
0
5.1
0
11.2
5.1
5.0
0
7.2
5.1
5.1
5.1
5.1
0.1
7.8
0.8
5.1
5.1
0
0
F1
IC551, 553: SN74AHC1G00DCKR
IC552: SN74AHC1G86DCKR
IC554: SN74AHC1G32DCKR
2-Input NAND Gate
Single 2-Input Exclusive-OR Gate
2-Input or Gate
A
1
5
Vcc
A
1
5
Vcc
A
1
B
2
B
2
B
2
GND
3
4
Y
GND
3
4
Y
GND
3
IC557: SN74LV00APWR
IC559, 616: SN74AHC1G08DCKR
IC571: RH5RE58AA-T1-FA
Quadruple 2-Input Positive-NAND Gates
IC560: SN74AHCT08PWR
IC572: RH5RE39AA-T1-FA
Quad 2-Input And Gate
Voltage Regulator
1A
1
14
Vcc
V
IN
2
1B
2
13
4B
1A
1
14
Vcc
1B
2
13
4B
1Y
3
12
4A
1Y
3
12
4A
2A
4
11
4Y
2A
4
11
4Y
2B
5
10
3B
Vref
2B
5
10
3B
2Y
6
9
3A
2Y
6
9
3A
GND
7
8
3Y
GND
7
8
3Y
I
J
K
★ All voltages are measured with a 10MΩ/V DC electronic volt meter.
★ Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
O : USED / APPLICABLE
X : NOT USED
UR067100
UR237100
UR237100
UR237100
UR237100
UR237100
UR067100
UR237100
10/50
10/16
10/16
10/16
10/16
10/16
10/50
10/16
UR268100
UR268330
UR268330
UR268330
UR268330
UR268330
UR268100
UR268330
100/50
330/50
330/50
330/50
330/50
330/50
100/50
330/50
IC503: MBM29LV320BE90T
IC504: W986432DH-7
4Mbit Flash Memory
SDRAM
RY/BY
DQ15 to DQ0
VCC
1
DQ0
2
RY/BY
Buffer
VccQ
3
VCC
DQ1
4
VSS
Erase Voltage
Input/Output
DQ2
5
Generator
Buffers
GND
6
WE
DQ3
7
State
Control
DQ4
8
BYTE
VccQ
9
RESET
Command
DQ5
10
WP/ACC
Register
Program Voltage
DQ6
11
Generator
Chip Enable
STB
Data Latch
GND
12
Output Enable
CE
Logic
DQ7
13
OE
NC
14
VCC
15
DQM0
16
WE
17
Y-Decoder
Y-Gating
STB
CAS
18
RAS
19
Timer for
Low Vcc Detector
Address
CS
20
Program/Erase
Latch
X-Decoder
Cell Matrix
NC
21
A20 to A0
A22
22
A13
23
A-1
A12
24
A2
25
A3
26
A4
27
DQM2
28
Vcc
29
NC
30
DQ10
31
GND
32
DQ17
33
DQ18
34
POINT C-1 1/Pin 7, 2/Pin8 of CB505
VccQ
35
DQ19
36
DQ20
37
GND
38
DQ21
39
DQ22
40
VccQ
41
DQ23
42
Vcc
43
1 +5M
2 /RES
IC505: MB3516APF-G-BND
RGB Encoder
POWER ON
POWER OFF
(connect the power cable)
(disconnetct the power cable)
GND2
R-OUT
24
23
R-output
buffer
75 Ω drive
1 +5M
2 /RES
CSYNC
POWER ON
(connect the power cable)
Clamp
1
2
GND1
R-IN
1 +5M
IC531: TC74HC4051AFEL
Analog Multiplexer/Demultiplexer
2 /RES
INHIBIT
VCC
6
5
Vcc
A
11
POWER ON
LEVEL
(connect the power cable)
B
10
CONVERTER
4
Y
C
9
GND
8
VEE
7
IC573: SN74AHCT126PW
0
13
Quadruple Bus Buffer Gates with 3-state Outputs
1
14
2
15
3
12
1A
1
14
VCC
4
1
3
V
OUT
1Y
2
13
6A
5
5
6
2
2A
3
12
6Y
7
4
2Y
4
11
5A
3A
5
10
5Y
INPUT STATES
INHIBIT
C
B
A
3Y
6
9
4A
1
GND
0
0
0
0
0
0
0
1
GND
7
8
4Y
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
X
X
X
L
M
N
IC502: YGV619
Advanced Video Display processor 6
D31-0
A23-2
CSREG
CSMEM
DREQ
RD
DRAWING
CPU
A1/WR3
SDQ31-0
PROCESSOR
INTERFACE
UNIT
WR2-0
SA12-0
SBA1-0
WAIT
SDRAM
READY
INTERFACE
SCS
INT
RAS
RESET
CAS
WE
SYCKIN
DQM3-0
SYCKOUT
SDCLK
VIDEO
CAPTURE
FSC
CONTROLLER
CSYNC
HSYNC
HSIN
CRT
CONTROLLER
VSIN
AT1-0
DCKIN
GCKOUT
DCKOUT
PIXEL
DRO[5:0]
GCKIN
DATA
CONTROLLER
DGO[5:0]
DRI[5:0]
DBO[5:0]
DGI[5:0]
DAC
DBI[5:0]
R, G, B
86
GND
CLK
CLOCK
85
DQ15
BUFFER
84
GND
CKE
83
DQ14
82
DQ13
81
VccQ
80
DQ12
CS
CONTROL
SIGNAL
79
DQ11
MONITOR
RAS
78
GND
COMMAND
77
DQ10
DECODER
CAS
76
DQ9
COLUMN DECODER
COLUMN DECODER
75
VccQ
WE
74
DQ8
73
NC
72
GND
CELL ARRAY
CELL ARRAY
A10/AP
71
DQM1
BANK #0
BANK #0
70
NC
69
NC
MODE
REGISTER
68
CLK
A2
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
67
CKE
BUFFER
A22
66
A11
65
A10
64
A9
63
A8
62
A7
DQ0
DATA CONTROL
DQ
61
A6
|
CIRCUIT
BUFFER
DQ31
60
A5
59
DQM3
REFRESH
COLUMN
58
GND
COUNTER
COUNTER
DQM0~3
57
NC
56
DQ31
55
VccQ
54
DQ30
53
DQ29
52
GND
COLUMN DECODER
COLUMN DECODER
51
DQ28
50
DQ27
49
VccQ
CELL ARRAY
CELL ARRAY
48
DQ26
BANK #0
BANK #0
47
DQ25
46
GND
45
DQ24
SENSE AMPLIFIER
SENSE AMPLIFIER
44
GND
IC511 - 516, 521 - 526: SN74LV245APWR
Octal Bus Transceiver with 3-state Outputs
G-OUT
B-OUT
VIDEO-OUT
Vcc2
N.C.
Y-TRAP
Y-OUT
CROMA-OUT
N.C.
N.C.
22
21
20
19
18
17
16
15
14
13
DIR
1
20
G-output
B-output
VIDEO
Y-output
CROMA
A1
2
19
buffer
buffer
output buffer
buffer
output buffer
75 Ω drive
75 Ω drive
75 Ω drive
75 Ω drive
75 Ω drive
A2
3
18
Y/C
MIX
A3
4
17
buffer
Y
A4
5
16
M
a
R-Y
6
15
t
LPF
R-Y
A5
r
modulation
i
x
B-Y
A6
7
14
LPF
B-Y
modulation
CSYNC
CSYNC
A7
8
13
Burst generation
Phase
Clamp
Clamp
LPF
& NTSC/PAL
A8
9
12
generation
selection
GND
10
11
3
4
5
6
7
8
9
10
11
12
G-IN
B-IN
N.C.
fsc-IN
NTSC/PAL-IN
N.C.
N.C.
CSYNC-IN
N.C.
Vcc1
IC532 - 536: SN74LV573APWR
Octal Transparent D-Type Latches
with 3-state Outputs
16
OE
1
20
V
CC
1D
2
19
1Q
BINARY TO 1-OF-8
2D
3
18
2Q
DECODER WITH INHIBIT
3D
4
17
3Q
4D
5
16
4Q
5D
6
15
5Q
COM
SW
3
6D
7
14
6Q
SW
7D
8
13
7Q
SW
SW
8D
9
12
8Q
SW
GND
10
11
LE
SW
SW
SW
1
OE
11
LE
"ON" CHANNNEL
C1
19
0
2
1D
1D
1
2
3
4
5
To Seven Other Channels
6
7
NONE
Vcc
OE
B1
B2
B3
B4
B5
B6
B7
B8
1Q

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