Baseband Processor Introductions - LG -S310 Service Manual

3. TECHNICAL BRIEF

3.4 Baseband Processor Introductions

3.4.1 General Description
Figure 2 depicts the block diagram of MT6235. Based on a dual-processor architecture, MT6235 integrates
both an ARM926EJ-S core and a digital signal processor core. ARM926EJ-S is the main processor responsible
for running high-level GSM/GPRS protocol software as well as multi-media applications. The digital signal
processor manages the low-level MODEM as well as advanced audio functions. Except for a few mixed-signal
circuitries, the other building blocks in MT6235 are connected to either the microcontroller or the digital
signal processor. MT6235consists of the following subsystems:
Microcontroller Unit (MCU) Subsystem: includes an ARM926EJ-S RISC processor and its
accompanying memory management and interrupt handling logics;
Digital Signal Processor (DSP) Subsystem: includes a DSP and its accompanying memory, memory
controller, and interrupt controller;
MCU/DSP Interface: the junction at which the MCU and the DSP exchange hardware and software
information;
Microcontroller Peripherals: includes all user interface modules and RF control interface modules;
Microcontroller Coprocessors: runs computing-intensive processes in place of the Microcontroller;
DSP Peripherals: hardware accelerators for GSM/GPRS/EDGE channel codec;
Multi-media Subsystem: integrates several advanced accelerators to support multi-media
applications;
Voice Front End: the data path for converting analog speech to and from digital speech;
Audio Front End: the data path for converting stereo audio from an audio source;
Baseband Front End: the data path for converting a digital signal to and from an analog signal from
the RF modules;
Timing Generator: generates the control signals related to the TDMA frame timing; and,
Power, Reset and Clock Subsystem: manages the power, reset, and clock distribution inside MT6235.
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