Table of Contents
Advertisement
Pin No.
Pin Name
82
R/C
83
G4
84
G3
85
G2
86
G1
COMPOSITE
87
SYNC. (INV)
88
—
89
POWER FAIL
90
IIC CLOCK
91
IIC DATA
92, 93
S9, S8
94
S7/FLD ENABLE
95
S6/FLD CLOCK
96
S5/FLD DATA IN
97
S4/FLD DATA OUT
98 ~ 100
S3 ~ S1
I/O
1. This pin receives remocon data through RC5F1, which amplifies and detects the
R/C signal.
I
2. After input signal is decoded in µ-COM (IC501), and performs related key
operation.
O
For LED clock model.
1. Input C-Sync (composite sync) to confirm whether video signal is present or not.
I
2. Confirms by counting 1H (63.5µsec) horizontal sync for a fixed time period.
—
Not connected.
1. When a power failure is detected, this pin goes "L" and the following sequence of
events occurs.
2. Power failure detector timing sequence.
AC POWER ON
Vcc for (Back-up)
AVcc No (Back-up)
I
Power failure signal
10MHz OSC
36.768kHz OSC
Reset pulse
Power failure
compensation relation
O
A reference CLOCK for Hi-Fi, TU/IF, MTS, SPEAKER
O
A reference DATA for Hi-Fi, TU/IF, MTS, SPEAKER
O
For LED clock model.
O
Outputs chip enable signal for FLD Drive IC (IC5F1).
O
Outputs clock signal to operate FLD Drive IC (IC5F1).
I
Serial interface signals for FLD Drive IC control.
O
O
For LED clock model.
36
Description
AC POWER OFF
5.3VA
Normal
Power failure
operation
compensation
state
state
(µ-COM memory loss state)
t
t
t
t
t
t
Power failure
compensation cancel state
Advertisement
Table of Contents
