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Circuit Diagrams and PWB Layouts45
ACS Module
1
2
3
4
H3
H3
ACS Module
A
2312
100n
B
7301
RESET TESTPOINT
TPS3707-33D
F301
RESET
1302
+9V
1
MR_
1
RT-01T-1.0B
C
3333
4
PFI
2K2
D
RESET
3331
Reset_ST
1-I2
100R
E
Reset_N
2-I15
F
IIC BUS
G
+5V
H
4302
Txd
2-K3
4303
SCL_A
NOT USED
2-I15
4305
SDA_A
2-H15
NOT USED
I
4304
J
K
F027
3201
SDA_B
2-M3,1-G2
100R
F028
3200
SCL_B
2-J3,1-G2
100R
L
+5V
M
SDA_C
2-H15,1-D2
SCL_C
2-H15,1-D2
N
O
P
3135 013 3233.3
1
2
3
4
DPTV465
5
6
7
8
9
+3.3V
2
14K
VDD
RESET 8
RESET
LOGIC&
RESET_ 7
TIMER
6
REF VOLT
NC
OF 1.25V
PFO_ 5
GND
3
SCL_A_Txd
1-C2
SDA_A_Rxd
1-C2
Rxd
2-J3
I2C BUS B
TEST CONNECT
1300
JQ-S
1
SDA_B
2
GND
SYNC_V
3
2-K15,1-I2
SCL_B
3349
OPTT
2-K3,1-N8
100R
SH_CLEAR
2-E18
3351
ADC_IN
2-D18
100R
5
6
7
8
9
7.
61
10
11
12
13
3329
RED_ST
1-N15
1K0
3328
GRN_ST
1-N14
1K0
3327
BLUE_ST
1-N14
1K0
3326
BLANK_ST
1-N8
1K0
3348
100R
1301
1
3350
2
COMPUTER
3
DEVELOPMENT
100R
4
CONNECTOR
5
6
B6B-EH-A
ADC_GND
AUTO CONVERGENCE
10
11
12
13
14
15
16
17
18
OSD "OR" CIRCUIT
+5V
7014
BC847B
3314
F023
R
1-E2
47R
+5V
7015
BC847B
3315
F024
G
47R
1-E2
+5V
7016
BC847B
F025
3316
B
47R
1-E2
+5V
7017
BC847B
3317
F026
BLANK
1-F2
47R
14
15
16
17
18
19
20
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
E_15000_038.eps
191004
19
20
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