STR-DA9000ES
QQ
3 7 63 1515 0
Pin No.
Pin Name
53, 54
BFSX0, BFSX2
55
HRDY
56
DVDD (3.3V)
57
VSS
58
HD0
59, 60
BDX0, BDX2
61
IACK
62
HBIL
63
NMI
64, 65
INT0, INT1
66
INT2
67
INT3
68
CVDD (1.8V)
69
HD1
70
VSS
71
BCLKX1
72
VSS
73
BFSX1
74
BDX1
75
DVDD (3.3V)
76
VSS
TE
L 13942296513
CLKMD1 to
77 to 79
CLKMD3
80
HPI16
81
HD2
82
TOUT0
83
EMU0
84
EMU1/OFF
85
TDO
86
TDI
87
TRST
88
TCK
89
TMS
90
VSS
91
CVDD (1.8V)
92
HPIENA
93
VSS
94
CLKOUT
95
HD3
96
X1
97
X2/CLKIN
98
RS
www
99 to 104
D0 to D5
105
A16
106
VSS
.
107 to 110
A17 to A20
144
http://www.xiaoyu163.com
I/O
I
Frame sync signal input terminal Not used
O
Ready signal output to the i. link system controller
—
Power supply terminal (+3.3V)
—
Ground terminal
I/O
Two-way data bus with the i. link system controller
O
Serial data output terminal Not used
O
Interrupt acknowledge signal output terminal Not used
I
Byte identification signal input from the i. link system controller
I
Non-maskable interrupt input terminal Not used
I
Interrupt signal input terminal Not used
I
Interrupt signal input from the HINT/TOUT1 (ta pin)
I
Interrupt signal input terminal Not used
—
Power supply terminal (+1.8V)
I/O
Two-way data bus with the i. link system controller
—
Ground terminal
I
Transmit clock signal input terminal Not used
—
Ground terminal
I
Frame sync signal input terminal Not used
O
Serial data output terminal Not used
—
Power supply terminal (+3.3V)
—
Ground terminal
I
Clock mode selection signal input terminal Not used
I
HPI 16 bit selection signal input terminal Not used
I/O
Two-way data bus with the i. link system controller
O
Timer output terminal Not used
I
Not used
I
Not used
O
Not used
I
Not used
I
Not used
I
Not used
I
Not used
—
Ground terminal
—
Power supply terminal (+1.8V)
I
HPI module selection signal input terminal Not used
—
Ground terminal
O
Master clock signal output terminal Not used
I/O
Two-way data bus with the i. link system controller
O
System clock output terminal (20 MHz)
I
System clock input terminal (20 MHz)
I
Reset signal input from the i. link system controller "L": reset
I/O
Two-way data bus terminal Not used
O
Address signal output terminal Not used
x
ao
y
—
Ground terminal
i
O
Address signal output terminal Not used
http://www.xiaoyu163.com
8
Description
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3
6 7
1 3
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2 9
9 4
2 8
1 5
0 5
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2 9
9 4
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9 9
2 8
9 9