Interrupt Status Register; Unique Address Register - NCR PC4I Technical Reference

DLC INTERFACE
SVCRQ
Service Request. This bit is used for transfer under
direct microprocessor control, that is, when the
Transmit Hold Register is waiting for a byte of data
(transmit mode) or when a byte of data is waiting to
be read from the Receive Hold Register (receive
mode). An interrupt is generated when this bit is
set.
With the exception of SVCRQ reading the Status
Register resets all its bits. SVCRQ is reset only
after the data transfer via the bus has occurred.
Interrupt Status Register
Three bits of the Interrupt Status Register read via
port 389H are significant:
Bit 0
Bit 1
Bit 2
A DLC controller interrupt sets this bit.
4 ms timer interrupt.
Reflects DRQ/IRQ jumper selection:
0 - DRQ2 and IRQ2
1 - DRQ1 and IRQ3
Unique Address Register
This register identifies the NCR PERSONAL COMPUTER in
the DLC configuration. Normally, the computer will be
functioning as the primary unit. The Unique Address
Register is automatically set to 01 (primary) at DLC
reset (which should always be performed after power
introduction and before a new command), so that this
register need not normally be written. If you have
cause to use your NCR PERSONAL COMPUTER as a seconda-
ry device in a DLC configuration, you can write this
register with a binary value as shown in Figure 5.7.
I
Bite
I 7 6 5 4
I
3
2
1
D
I
I
I< Terminal Number 1-31
>
D D
1
I
(D
= primary)
Figure 5.7 Unique Address Register
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