Block Diagram - Yamaha CD-S3000 Service Manual

A B

■ BLOCK DIAGRAM

1
Loader mechanism unit
2
COAXIAL
DIGITAL
OUT
OPTICAL
COAXIAL
DIGITAL
3 IN
OPTICAL
• See page 61–63 →
DIGITAL
SCHEMATIC DIAGRAM
4
+3.3USB +1.5USB
UPD800500F1-011
LCO
Pin [10]: VBUS
3.3V
USB
Pin [15,17]: DP,DM
DP_USB_B
DM_USB_B
5
Pin [23,24]: XO,XI
D1 C1
XL402
SYS1_TXD,SYS1_RXD, 12.288MHz
SYS1_RTS,SYS1_CTS
EN29LV160CB-70T
SYSTEM
CONNECTOR
6
CLAMP_MTR1,2
Tray
TRAY_MTR1,2
Motor
Driver IC
• See page 66–68 →
7 FRONT
SCHEMATIC DIAGRAM
C D
Y101
27Hz
SA-CD
Module
DOUT
PI_BCK_DSDCLK
PI_WCK
PI_SDO_DSDL
PLL
PI_DSDR
Clock
Recovery
PI_BCK_DSDCLK
PI_WCK
PI_SDO_DSDL
PI_DSDR
DIT
SSP2_SDO0
SSP2_WCK
SSP2_BCK
DIR/DIT
SSP2_MCK
PCM9210PTR
39 40
XL403
24.576MHz
SSP2_SPDIF
F3: DIT0
IC401
SSP2_SDO1
A5: SDO1
SSP2
SSP2_SDO0
D6: SDO0
SSP2_WCK
E1: WCLK0 +3.3USB +3.3D
SSP2_BCK
E3: BCLK SW
SSP2_MCK
F1: SYSCLK
+1.5USB
1.5V
SSP2_YOSI
Regulaotr
G2: Serial Port RXD.
SSP2_YISO
G1: Serial Port TXD.
SSP2_YOSI_N_IR
H1: IRQN_IN
SSP2_YISO_N_IRQ
H2: IRQN_OUT
SSP2_YOSI_MUTE
F4: MUTEN
SSP2_USB_RDY
K4: PEO3
SSP2_YISO_MUT
J4: PEO2
SSP2_YISO_DSD_PCM
J3: PEO1
SSP2_N_IC
J1: ICN
SSP2_N_DSPSTOP
H4: DSPSTOP
R21 R22
XL404
IC413 30MHz
Flash ROM 16Mbit
LOAD+,LOAD-
87,88
CLAMP_SW, UNCLAMP_SW
TRAY_SW, TROPEN_SW, TRCLOSE_SW
38-40
CLAMP_MTR1,2
44,45
TRAY_MTR1,2
42,43
Clamp
Motor
Driver IC
3.3V 5V
Convert
+5V
POWER
Regulator
FL
IC911
IO Expander
LC709004AMJ-AH
E F
+5MO1
+5MO2
+7MT
CD_SPDIF_RQ
CD_PWR_DET
CD_RST
CD_PWR
CD_MUTE
CD_YOVI
CD_YIVO
IC443
FPGA
LATTICE
LCMXO2-640HC
MAIN
DIR_MCK
OUTPUT
DIR_BCK
PORT
DIR_WCK
DIR_SDO
DIR_SPDIF
SSP2_SDO1
FPGA_BCLK_DSDCLK
SSP2_SDO0
FPGA_WCLK_DSDL
SSP2_WCK
FPGA_SDO_DSDL
SSP2_BCK
FPGA_SDO_DSDR
SSP2_MCK
FPGA_SPDIF_DSDR
SSP2_SPDIF
MPO0/1
SEL
FPGA_JTAGEN
FPGA_PROG
FPGA_DONE
FPGA_INTN
IC424
FPGA_SEL_C
FPGA_SEL_B
FPGA_SEL_A
FPGA_RRESET
FPGA_DOP_DSDRATE
FPGA_DOP_DSDPCM
FPGA_DSDMUTE
+3.3D
+5D
+3.3D
+3.3M
IC404
Microprocessor
M16C/64A
R5F364AENFA
13 15
XL401
20MHz
PURE
SOURCE
DIRECT
G H
+12L
+3.3L DAC 3.3V Shunt
+1.2L
DAC 1.2V
AGNDL
Shunt
-12L
RY3
DAC1
DAC3
DAC5
24 DAC7
XL1
IV Convertor
40MHz
RY3
DAC1B
DAC3B
DAC5B
BCLK/DSDCL
DAC7B
DATA__CLK
RY1
WCK/DSDL
DAC1
IC8
ESS9018
SDO/DSDL DAC3
DAC5
RY2
DAC7
SDO/DSDR
DAC2
DAC4
DAC6
DAC2
DAC4 RY4
SPDIF/DSDR
DAC6
DAC8
VDDT
IV Convertor
VDD
DAC2B
DAC4B RY4
DAC_SCL
DAC6B
DAC_SCA
DAC8B
DAC_N_RST
+12R
DAC 1.2V
+3.3R
DAC 3.3V Shunt
+3.3D
DAC 1.2V
+1.2L
AGNDR
Shunt
-12R
POWER
TRANSFORMER
+5MO1
+5MO2
DGND
+12D
+12RY
CGND
-12RY
+7MT
MGND
+30VP
FL_PON
FLGND
83 PRVD
FL1,2
PRVL
82
+12L
AGNDL
PRVR
81 -12L
+12R
AGNDR
-12R
PDET
RESET
Writing port
+3.3M
+10S
+3.3M
REG
+3.3S
I J
CD-S3000
BALANCED
L
OUT
L
ANALOG
OUT
R
BALANCED
R
OUT
• See page 64, 65 →
AUDIO
SCHEMATIC DIAGRAM
RY902
AC IN
47