Dtv Main Chipset - Samsung LE23R86BD Service Manual

13-4 DTV MAIN ChipSet

13-5-1 STx5105 SPEC.
Enhanced ST20 32-bit VL-RISC CPU
- 200 MHz, single cycle cache/4 Kbyte instruction cache,/
4 Kbyte data cache, 2 Kbyte SRAM
Unified memory interface
- Up to133 MHz,16-bit wide DDR SDRAM interface
Programmable flash memory interface
- 4 separately configurable banks, 8/16-bits wide
- SRAM, peripheral, Flash, SFlash
- Support for low cost DVB-CI
Programmable transport interface (PTI)
- Single transport stream input
- Support for DVB transport streams
- Integrated DVB, ICAM descramblers
MPEG-2 MP@ML video decoder
- Fully programmable horizontal and vertical SRCs
Graphics/display
- 4 display planes
- 8 bpp CLUT graphics, 256 x 30 bits (AYCbCr) CLUT
entries. 16 bpp true color graphics, RGB565,
ARGB1555, ARGB4444 formats. Link-list control
- Alpha blending, antialiasing, antiflutter, antiflicker filters
- 2D paced blitter engine with fill function
- Blitter based display compositor
support
PAL/NTSC/SECAM encoder
- RGB, CVBS, Y/C and YUV outputs with four 10-bit DAC
outputs. RGB/CVBS or YUV/CVBS or YC/CVBS.
- Encoding of CGMS, Teletext, WSS, VPS, close caption
Audio subsystem
- MPEG-1 layers I/II
- Simultaneous MPEG audio decode and output of Dolby
streams on S/PDIF
- IEC958/IEC1937 digital audio output interface
- Integrated stereo audio DAC system
Central DMA controller
On-chip peripherals
- Two ASCs (UARTs) with Tx and Rx FIFOs
- Three 8-bit banks of parallel I/O and one 7-bit bank
- One smartcard interface and clock generator
- Two SSCs for I©÷C/SPI master/slave interfaces
- Infrared transmitter/receiver
- Integrated VCXO
- Low-power / RTC / watchdog controller
JTAG/TAP interface
Package 23 x 23 PBGA
13 Circuit Descriptions
13-9