Display Control Non Full-Hd Sets With Fpga; Block Diagram Display Control Non Full-Hd Sets With Fpga - Philips FJ3.0E Service Manual

EN 228 9. FJ3.0E LA
• Scaling of input signals to output in case not an 1080i
signal is received.
• Deinterlacing of input signals to output in case an 1080i
signal is received.
• Additional sharpness improvement.
• AmbiLight drive (3 or 4 regions).

9.11.2 Display Control Non Full-HD sets with FPGA

VIPER
PNX2015
Spider I
In non full-HD sets with an FPGA, the video signal coming from
the Viper is directly fed to the Pacific 3 through an CMOS
connection. The FPGA however is used for AmbiLight
processing through an I
Backlight is coming from the Pacific 3 and can be analogue or
pulse-width modulated, depending on which display is used.
The signal for Scanning Backlight is an I
Viper. The MOP interfaces:
• CMOS video input.
2
• I C output for driving the AmbiLight unit.
• Additional configuration flash memory.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
MOP2K6-
AMBI
Spartan 3E
JUMPERS
CMOS
Select-AnaPWM Dimming
I2C-Scanning (no dimming)
Figure 9-10 Block diagram display control non full-HD sets with FPGA
2
C connection. The signal for Dimming
2
C signal coming from
• Pattern generator.
The MOP interfaces:
• CMOS video input, and dual LVDS output.
2
• I C output for driving the AmbiLight unit.
• Additional configuration flash memory.
• Field memory (SDRAM) for video processing part.
SPI-flash 2Mbit
M 2 5 P 2 0 -
V M N 6 T P
XCF02SVOG20C
SPI-flash
M25P05
Pacific 3
CMOS
I 2 C
PWM Dimming
MUX
Non 1080p Display
LVDS
1x
Vdisp / +12Vsw
LVDS
I2C4
AmbiLight
Level
shift
Analog/PWM
Dimming
Scanning
Backlight
G_15990_114.eps
100506