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A
B
C
D
E
F
G
H
H2
H6
H4
H8
2
4
6
8
RA13
D1H82204A024
1
3
5
7
FL8
F1H0J1050018
54
53
52
51
50
49
48
1
2
3
4
5
6
7
FL9
F1H0J1050018
2
4
6
8
RA15
D1H82204A024
1
3
5
7
H1
H5
H3
H7
A10
A2
A8
A3
A4
A5
A7
A6
C12
0.1
20
19
18
17
16
15
14
13
12
11
IC12
C0JBAZ001776
(74LCX541MTCX)
(DV I/O)
1
2
3
4
5
6
7
8
9
10
I1
I2
I3
I4
I5
I6
I7
I
I8
J
K
L
12
13
A11
A9
H10
H14
H12
H16
2
4
6
8
RA14
D1H82204A024
G2
G3
G7
1
3
5
7
G1
G5
G9
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
G4
G8
G6
G10
2 4 6 8
RA16
D1H82204A024
1 3
5
7
H9
H13
H11
H15
E1
E2
E3
E4
E5
E6
E7
E8
E9
K22
K23
K24
K25
K26
K27
K28
K29
DMR-HS2EB/EB1/EG/EG1/GN
AV-Decoder Section(Digital P.C.B.(3/7)) Schematic Diagram(AD)
14
15
16
G11
FL5
F1H0J1050018
29
28
IC4
C3ABPG000067
or C3ABPG000078
or C3ABPG000063
(64Mbit SDRAM)
26
27
FL6
F1H0J1050018
G12
LB1
J0JHC0000032
K34
K35
K36
FL25
F1H0J1050018
R55
R56
R2
R3
47
47
47
47
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
FL7
F1H0J1050018
FL1
F1H0J1050018
K21
K12
K9
K10
K11
K31
17
18
A1
F13
F9
F5
F1
F11
F7
F3
F15
2
4
6 8
2 4 6 8
RA9
RA10
D1H82204A024
D1H82204A024
1 3 5
7
1 3
5 7
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
2 4 6 8
2 4 6 8
RA11
RA12
D1H82204A024
D1H82204A024
1 3
5
7
1 3
5
7
F12
F8
F4
F14
F10
F6
F2
F16
FL3
F1H0J1050018
R4
22
16
15
14
13
16
IC1
C1DB00000895
(CLOCK GEN.)
9
10
11
12
1
C15
6V22
R60
47
K32
DMR-HS2EB/EB1/EG/EG1/GN
AV-Decoder Section(Digital P.C.B.(3/7)) Schematic Diagram(AD)
19
20
G
G2
G3
G7
G11
G1
G5
G9
37
36
35
34
33
32
31
30
29
28
IC2
C3ABPG000067
or C3ABPG000078
or C3ABPG000063
(64Mbit SDRAM)
18
19
20
21
22
23
24
25
26
27
G4
G8
G12
G6
G10
FL4
F1H0J1050018
15
14
13
12
11
10
9
IC9
C1DB00000950
2
3
4
5
6
7
8
R57
0
FL27
F1H0J1050018
K33
K14
21
22
A
B
C
D
E
F
G
H
I
J
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