Sub Cpu Operation (Interfacing With The Main Cpu) - Sharp PC-1600 Service Manual

-
PC-1600
4· 3 . Sub CPU operation
(Interfacing with the main CPU)
TC8576F (UART)
DSTB
BUSY
ACK
DATAS
DATAl
r-----------,
I
I
I
,
,
)0 _.
D7-
Buffer
<
bus) ,
(data
,
,
I
,
,
,
10RP
,
-_.-
(from SC7852)
~------r---~
Contained in the LR38041 gate array
Fig.4
Signals interfaced with the
R13~ROO, and R33~R20.
RI3-ROO=:>( Command
KI ~
~ ..... 'B~;;"
Z10
Ready
Z9
R33-R20
10RP
The following shows signal timings.
Send command
Read retu rn data
LU57813P (sub CPU)
KI
ZlD
Z9
Rl3~ROO
,
, I
,
....
-
'
R33~R20
,
I
,
I
f
main CPU are KI, Z10, Z9,
X' -
---r
Ready
=fJt
'9.5µ,
X
Return data
---------,
I
I
I
CD
Before the
CPU, the sub CPU is asked
command.
CPU becomes
The Z· 8 0 assumes
BUSY input of the UART is high.
®
Next, 8· b it
Z· 8 0
The sends the da ta on the DA TAl ~DA T A8 port
of the UART,
through R13~ROO.
second, the
®
Z· 8 0
The sends a pulse signal on DST8 of the UART in
order to inform
which the sub CPU receives of through
With the KI line of the sub CPU high, an interrupt
is se nt to the sub CPU, and the command
in the interrupt
G) One of the following
on the command
(i) Arequest
(ii) Arequest
The sub CPU then
the next step,
I
(i A pulse
return
of the command
(ii) A pulse
of the command.
In either case, the
_
state on Z9.
The high state
ACK line of the
Z· 8 0
checks the latch if it is okay.
®
Z· 8 0
When the
return data, it forces 10RP to low so that the LR38041
gate array internal
data (R33~R20)
-~-
Z· 8 0
CPU sends a command
if it is ready to receive the
If it is not, the Z· 8 0 waits
ready.
the sub CPU to be ready
command data are sent to the sub CPU.
wh ich are received by the
Unless ACK is returned
Z· 8 0
proceeds to the next processing.
the sub CPU a command
the Klline.
service routine.
requests may be made depending
Z· 8 0.
issued from the
for return data
not to return data
interprets the above to proceed
signal is sent on Z9 after
data on R33~R20, to indicate
execution.
signal is sent on Z9 to indicate
Z· 8 0
waits for a high pulse signal
received on Z9 is then
UART and latched
accesses 33H of 1/0 to request
buffer is opened to send the return
on the Z· 8 0 bus D7~DO.
to the sub
until the sub
if the
sub CPU
within one
request,
is processed
to
sending the
completion
receipt
input to the
internallv, The
the