Rs-232C Interface Signal - Sharp PC-1600 Service Manual

PC-1600
UART
Receive
data
At the same time the RS-232C interface is selected with a
high PRIME state, VDD is supplied from the high side of
the RS-232C interface.
The SIO interface is selected with a low PRIME state and
VDD is turned off. During the system on and reset, PRIME
is at low.
PRIME
------------------~
SO F (0_!_jIJJJJJ[j
~====--------------------------
murrrn
~~L_
ROF (I)
_n_,
TXO (0) -- -- --- - -- - - -- -
RX 0 (I)
n -- - -- - - -- -- - -- -
RTS (0)
CTS(I)
CO
(I)
OSR (I)
Cf (I)
OTR (0)
v
00 - - - - - - - - - - - - - - - - - - - - -
TXO(UAR~
UIIIIIIII
RXO (UARTJ
CD
When PR IME is at a low state, the RS-232C interface
outputs either in a high impedance or a low state (non-
active).
®
When PRIME is at a low state, the SIO interface
signals, SDF and RDF, are in an opposite polarity with
the UART
Input/output
start bit is high and the stop bit is low. So, both are
in a low state when no data are sent or received (UART
TXD and RXD are at a high level).
®
When PRIME is at a high state, both SDF and RDF are
at a low level and non-active (stop
@ When PRIME is at a high state, TXD and RXD of the
RS-232C interface are opposite in their
those of TXD and RXD of the UART.
@ When PRIME goes high, VDD is activated (RS-232C
interface high side voltage),
®
The RS· 2 32C interface
DSR, CD, and CI-are
polarity), regardless of the state of PRIME (high or
low),
7-7-1. RS· 2 32C interface signal
Although signals of this interface
standards, they are used for controls that differ in some
ways from the RS-232C interface in general.
R S· 2 32C
rm:rr:rnn
-;:::=========
rrnmunLU..Ll.ll.U.L_ __
-- -,
ummrn
lIIIIIllIII
signals, TXD and RXD. The
bit}.
as are
polaritv
signals-CTS,
input/output
to the UART (opposite
Input
conform to the EIA
(1) Input signals are received by the transistor
through
output
interface
to VCC using a resistor, as shown in the hybrid
IC BX7269W. A diode is inserted across the base and
emitter of the input which will bring the signal below
the GND level (stop
be at the GND level. Therefore,
converted
signal.
0 I
GND
__jU
(2) On the
through the circuit shown below (hybrid IC),
__
While the input level is CMOS compatible
the
output
The figure below illustrates this.
Vcc
Va
GND
VDD_j\
Vcc
00-
Vb
::: : :::-c- __ : -~:-~
1/0
::l I
Vc
VEE
CD
When the input (a) is low (GND), the level (b) is below
GND
and
level.
The MN4584 IC is a Schmitt inverter to which VDD
and VEE is supplied. This IC has a hvsteresis against
input.
Output
VEE
-14-
the open collector
etc.) and make it assume to
bit,
the input signal is
in the hybrid IC to be handled as a logic
-
~-GND
other hand, the
output
is converted to the VDD-VEE
~--~-~-~------~--~-~-V
y,""
-=~ ~ -::-
is assumed by the MN4584 to be at a low
VTHL GND VnlH VDD
and are
and pulled up
- __ Vcc
signal is
output
(0-4.7V),
level.
n n
n
Input