Sharp PC-1600 Service Manual page 69

PC-l600
TABLE· 3
I I
Port address
10Ra Addross
Ml A7 A4 A3 A2
A6 A5
1
1 0 0 0 0 0
0
0
0 0
0 0
'---
NOTE: Above are all high active as seen from the CPU side, except that FD reset is low active .
• Gate array (LR38045) pin description
Pin
Symbol
No.
1-8
PC7N - PCON
9 -16
PB7N - PBON
(NCI
17
18 PUl
19 PTI
20 EZI
MINI
21
10RQ
22
MRQI
23
24 RSTI
VCC
25
GNO
26
IRQ
27
28 RONI
29 WRNI
30- 39
AOI - A71
A141. A1SI
(NC)
40
41 RSTN
WR
RO Operation
Al AO
0 0 0 1 Write data to FFl
1 Read data f rom F F 1
0
1 Reset FO
0 0 1
(reset with "0")
1 0 Read PAO - 7
1 0 1 Write data to FFO
0
(PBO- 71
1 0 Read data f rom F FE
(PBO- 7)
1 1 1 Write data to FFE
0
(PCO-7)
Read data Irom F F3
1 0
(PCO-7)
Active
Level at reset
1'0
level
Out Low High
Out High
Low
In (Low)
In (High)
(High)
In
In (High)
In High
High
In
In High
High impedance
Out Low
In Low
In Low
In
Out Low Low
Table· l
07 D6
05
.
Printer CR Printer SW
0
INT INT
Enable Enable
t t t
CMT
(0) Printer Print
CR
input .
CMTin RMT RMT
Enable OFF ON
t
t t
Motor Motor Motor Motor
YD YB YC YA
t t t
8-bit outout port (port address:
DO - D7 correspond to PCO - 7Nvia
8-bit outpur port (port address:
DO - D7 correspond to PBO - 7N via FF2.
PU signal input.
[ Used for creation
PT signal input.
ELH signal input.
[ Used for creation
Ml signal input.
10RQ signal input.
MREQ signal Input (used for generation
Reset signal input.
When the reset signal is received on this line, it issues the internal
flipflop reset signal and RSTN (2.5"
~ Power supplv.
Interrupt signal outpur.
The output is N-channel
onthe PC-1600 side.
RO signal input.
WR signal Input,
Address Input.
2.5" F DO reset signal output,
The active state of the signal is unconditionally
signal and it must be cleared
to create the signal by software.
-66-
Oata
04
03 02 01
Reverse
FOINT PF key PF key
Enable INT
INT
Enable
Enable
t t t t
FO
Reverse
SW fNT PF kev PC key
Moto, Motor Motor
ZO ZB ZC
t t t t
Motor Motor Motor
XO XB XC
t t t t
Description
83H).
FF3'
82H).
of a 32KS ROM signal
(CSNO).
'of the 107N and gate
array internal enable signal.
of CSNO).
FDD reset signal).
open drain type and is pulled up to VCC
issued with areset
by means of software. It is also possible
(Address: 81 H, 00, WR)
00
CC key
INT
Enable
t
FO
Reset
CC
key
Motor
ZA
t
Motor
XA
t
J
J
I