Printed Circuit Board - Yamaha CDR-HD1000 Service Manual

A B
SCHEMATIC DIAGRAM (MAIN 1/2)
1
Q Q
3 7 6 3 1 5 1 5 0
2
3
4
T E
L 1 3 9 4 2 2 9 6 5 1 3
5
6
7
IC1: SN74LS06NSR IC4: PST572CMT-R
IC5 : IS41C16100S-50K
Inverter Buffer/Driver System Reset
1M x 16 (16-MBIT) Dynamic RAM
1A 1 14 VCC VCC 1
I/O0 2
1 Vcc
I/O1 3
1Y 2 13 6A
I/O2 4
I/O3 5
VCC 6
2A 3 12 6Y
3 Out I/O4 7
+ I/O5 8
2Y 4 11 5A
I/O6 9
I/O7 10
NC 11
3A w w w 5 10 5Y
NC 12
WE 13
3Y 6 9 4A RAS 14
2 Gnd
NC 15
8 NC 16
GND 7 8 4Y
A0 17
A1 18
.
A2 19
A3 20
VCC 21
9
C D E
CLOCK
2.6
0
2
2.5 2.5
1
3 5.1
2.5
5.1
0
2.5
2.5
2.6
0 2.4
5.1
0
1.7
1.1
5.1
0
5.1
0
5.1
2.5
0
0
0
0
2.6
2.5
2.5
2.6
2.5
2.5
2.5
0
0
2.3
2.6
5.1
5.1
1 1 0
0
-4.9 0
0
0.1 3 4 5.1
0 0.9
0 0
5.1 2.1
A
0 2.4
5.1 0.9
0 5.1
5.1 5.1
5.1 0
5.1 CPU 5.1
5.1 5.1
5.1 5.1
5.0 5.1
0 5.1
5.0 5.1
4.9 5.1
5.1 5.1
0 5.1
5.1 0
5.1 4.9
2.6 5.1
0 5.0
5.1
5.1 4.9
5.1 0
0 0.1
0 5.1
0 ~
5.1 3.8
IC7: MSM514260E-60JS
4Mbit DRAM
OE
42 GND
Timing
41 I/O15 WE RAS 14
Generator
40 I/O14
CAS WE OE
39 I/O13 LCAS
CLOCK CONTROL CONTROL LCAS
38 I/O12 CAS WE 29
UCAS
GENERATOR LOGICS LOGIC
37 GND
UCAS 28
36 I/O11
35 I/O10
34 I/O9
RAS DATA I/O BUS
33 I/O8
RAS CLOCK 9
32 NC
GENERATOR
31 LCAS COLUMN DECODERS
30 UCAS
29 OE SENSE AMPLIFIERS
x a o u 1 6 3
28 A9
y A0~A8
REFRESH
27 A8
COUNTER
26 A7 I/O0~I/O15
25 A6
i
24 A5
23 A4 9
MEMORY ARRAY
22 GND ADDRESS
1,046,576 x 16
BUFFERS
A0~A9
VCC 20
VSS
21
F G
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8
~
1.3
5.1
0
5.1
~
0
~
4.9
0
B 0
ACDR ~
5.1
0
~
5.1
~
~
~
~
~
5.1
5.1
2.6
2.6
2.6
2.6
2.6
2.6
2.6
0
0
2.6
2.6
2.6
2.6
2.6
2.6
2.6
2.6
C
Ch 1
Q Q
Ch 2 3 7 6 3
5.1
5 6 1 8
5.1 5.1 0.2 0.2 4.8
0
0.2 9 2 5.1
SYSTEM
5.1
RESET 5.1
14
5.1
11 10 11 10 3
5.1 0 5.1 5.1
5.1
5.1
14
0.2 6
5
5.1
7
0
0.2 5.1
13 12
FLASH MEMORY
5.1 0 5.1
12 13 8 9
1.6 2.0
2.3 5.1
3.0 0
5.1 0 1.7 0.9
1.7 0.9 1.3 1.4
1.9 2.4 1.4 2.4
1.9 2.1 1.7 1.3
1.8 0.9 2.4 2.1
5.1 0 1.6
1.8 1.3 0.9
1.6 1.2 4.9 1.8
1.3 1.4 5.1 5.1
1.4 2.6 1.3
1.8
0
3.4 1.2
4.8 3.4 2.3 1.9
1.4 0 3.8 1.4
1.7 2.6 1.9
2.4 2.5 2.6
2.2 2.6 2.5 1.7
2.3 2.5 2.5 4.9
2.4 2.5 2.7 0
2.7 2.5 2.4 5.1
5.1 0 2.3 2.2
DRAM
IC8: TC74HC14AF-TP1
Inverter
WE OE
13 27
1A 1
I/O
Controller 1Y 2
Output
8 8
I/O Buffers 3
2A
Controller
DQ1~DQ8
2Y 4
Column
Input
Address 9 Column Decoders
8 8
Buffers
Buffers
3A 5
I/O
Internal
Sense Amplifiers 3Y 6
Refresh 16 Selector 16
Addess
Control Clock
Counter
GND 7
Input
8
8
Buffers .
Row
Row
Address 9
Word Memory DQ9~DQ16
Deco-
Buffers
Drivers Cells
ders
Output
8
8 Buffers
On Chip
VBB Generater
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H I
2 4
9 9 8
DRAM
5.1 0
5.1 ~
5.1 ~
5.1 ~
5.1 ~
5.1
5.1 2.2
5.1 ~
5.1 ~
5.1 2.2
5.1 2.5
5.1 5.1
~
5.1 ~
5.1 ~
5.1 ~
5.1 ~
5.1 0
1 5 1 5 0 8 9 2 4
4
0
IC11: MBM29F800BA-70PFTN
8Mbit Flash Memory
VCC
VSS
WE
BYTE
RESET
CE
IC9: TC9246F-TEL OE
Clock Generator
VDD LOCK S2 S1 M2 M1 CKO VSS
16 15 14 13 12 11 10 9
14 VCC
13 6A
Lock
µ-COM Interface
Detector
12 6Y
Programable Counter
11 5A
VAR
m
10 5Y
Phase
VCO Selector
Comparator
REF A0 to A18
9 c o 4A
A-1
8 4Y
1 2 3 4 5 6 7 8
REF PD VDDA AMPI AMPO VSSA XI XO
All voltage are measured with a 10MΩ /V DC electric volt meter.
Components having special characteristics are marked s and must be
replaced with parts having specifications equal to those originally
installed.
Schematic diagram is subject to change without notice.
J K L
CDR-HD1000
Pin 74 of IC2
Point A
2
9 9
B Pin 129 of IC3
Point
VCC of IC4
Point C
and OUT of IC4
POWER ON
9 8 2 9 9
IC202: NJM2904M
Dual OP-Amp
V–
Q6
Q2 Q3 Q5
– Q1 Q4
Q7
INPUTS
OUTPUT
Q13
+
Q11
Q12
Q10
Q8 Q9
RY/BY DQ0 to DQ15
RY/BY
Buffer
Erase Voltage Input/Output
Buffers
Generator
State
Control
Command
Register
Program Voltage
Generator
Chip Enable STB
Data Latch
Output Enable
Logic
Y-Decoder Y-Gating
STB
Timer for
Address
Low Vcc Detector
Program/Erase
Latch
8,388,608
X-Decoder
Cell Matrix
E-34/J-32