Operating Principle; Basic Principle Of Operation; Description Of The Block Diagram - Philips PM 5390 Service Manual

2-1
2.
OPERATING PRINCIPLE
2.1.
basic
PRINCIPLE
OF
OPERATION,
fig.
30
a
The
operation of the
PM
5390
1
GHz RF
synthesizer
is
based
on
the
principle of indirect
synthesis;
frequencies are
generated
by
VCOs
(Voltage Controlled Oscillators) in
digital
Phase-Locked Loops
(PLL).
Four
of
the
six
frequency ranges
-for
frequencies
from 340
to
1020
MHz-
are
generated
by the maid
oscillator
VCO
la
...
Id.
Mixer
oscillators
VCO
2a and 2b generate
4 fixed frequencies for mixing
with
the corresponding
4 frequency
ranges of the main
oscillator.
The
two lower frequency ranges
from
0.1 to
340
MHz
are
generated
by mixing
VCO
la or
VCO
(assisted
by
VCO
2 just
mentioned) with the fixed
510
MHz
frequency
of
VCO
3.
For
this
the output
signal
is
switched to mixer
2.
All
3
oscillators
VCO
1,
VCO
2 and
VCO
3 are related to the
5
MHz
X-tal
reference oscillator
.
Frequency control operates
by comparing the output signal
from
VCO
1,
mixed with the
relevant
frequency generated
by
oscillator
VCO
2,
with
a signal
from the reference oscillator.
Both
signals
are
divided
down
to
1
kHz
-
the reference signal
by
a
fixed reference divider
and the
output
signal
by a
programmable divider controlled via
ports
by the microprocessor.
Also
in
phase-locked loop 2 the frequency
is
controlled via
ports
by
setting
the division factor of divide
r
2,
in
this
case to
4
values for
the
4 fixed frequencies.
Frequency
synthesizer
HEF
4750
and programmable
divider
1,
HEF
4751, are
two
ICs
matched to each
other. Divider
1
provides a 'fast
output'
FF
to allow
fast
frequency
locking
and
a
'slow
output'
FS which
is
used
for fine
phase control.
2.2.
description
OF THE BLOCK DIAGRAM,
fig.
30
The
instrument
works under
control of the
8085
microprocessor within the central processing
unit,
CPU. The program
memory
consists of
two
EPROMs.
On
the data
memory
chip
two
further functions
are
implemented,
i.e.
a
timer
,
generating
sweep
control signals,
and 12 output ports for the
modulation
modes on
the
modulation
interface. In
the long-term data
memory
up
to
8 complete parameter
settings
of
the instrument can be
stored
and
recalled.
For
this
the
BATTERY
switch at
the
rear
panel
must
be
set
to
'1'
(ON).
The low-power
CMOS RAM
is
backed-up
by
a
NiCd battery pack.
It
ensures storage
after
mains
switch off
or
in
case of mains
failure.
Ports
2 and 3
on
unit
2 and port
1
on
unit
1
control
all
circuitries
on
the various units.
The
keyboard/display unit
5 contains
all
display
elements
and
switches (keys).
Together with unit
4
it
forms
a
sandwich pack.
The
central circuit
on the kevboard/display
interface unit
4
is
the micropro-
cessor controlled
keyboard
controller.
This interface
component produces the scan
signals
for
the key-
board
matrix
and
picks
up
the return
lines,
sends the data
information for
the 7-segment
displays
and
controls the multiplex lines
for the display
positions.
The
I
EC
bus
interface
is
built-up in
standard configuration.
The
data, transfer control
and
management
signals
are transferred via a flat
cable
from
the
IEEE
bus connector
on
the small unit
6
at
the rear
of
the instrument to the interface.
The
address switches are also
attached to the small rear unit.
The
operating principle
of the
oscillators
VCO
1
.
VCO
2 and
VCO
3
was
already described
in
the pre-
vious chapter
2.1.
The output of the
main
oscillator
VCO
1
is
fed to the
automatic
level
control.
Afn-
plitude
modulation
can
be added
after this stage.
Video modulation
is
also
applied here.