Table of Contents
Advertisement
3-14
3,5.5.
Sweep
frequency
generation
As
mentioned
the
frequency
of
the
main
oscillator
is
set
by
the
programmable
divider
in
the
main PLL
system
(unit
2).
A
sweep
is
generated
by
stepwise changing the
division factor:
in
equal
time
distances
(t
sweep/50) the
division factor
is
increased
by
a
constant
calculated value
and
read-in.
The
increase
ef
the
factor
can be
1
...
1000, corresponding
to
frequency changing
of
(1
...
1000) x
1
kHz
per
step.
A
start
pulse
IRQ
sweep
for setting
the next
division factor
of the
PLL
loop
is
sent to the
interrupt
input
RST
5.5 of the microprocessor.
The
processor
counts
50
pulses
and
resets
the system.
The
Input
sequence
for reading
the
division factor Into
the prog,
counter
is
controlled
at
input
PC
by
the 3
MHz
processor clock divided to
130
kHz
by
the
23
:
1
divider
4,
1C
307
/
U2. Program
enable,
PE,
starts
the
process.
Taking
the processor clock
assures
a
synchronous
handling of the
division factor
with
PE
and
PC.
The
figure
below
also
shows
the generation of the
sweep
time.
The
set
sweep
time
is
converted
by
the
processor
into
a
division factor
N
of the timer
circuit
within 1C
318
/U1.
At
each
setting
of
a
new
frequency
(IRQ
sweep,
see
above) the
TCU
signal
increases
the
state
of the binary
counter
312/U2
by
1.
6 output
lines
are
connected
to the
summing
point of the operational amplifier
304
via resistors
643
-
648,
the values of
which
are
binary weighted.
So
the
output
of 1C
304
shows
a staircase
signal.
The
output
is
connected
to the
SWEEP
TIME
OUT
socket
at
the
rear
of the instrument,
where
a stair-
case
voltage
from 0
to
500
mV
in
50
steps
of
10
mV
each
is
available;
the period of the
staircase
ramp,
i.e.
the
sweep
time, to
which
200 ms
fly-back
time
must
be added, can be
set
from
0.05
s
to
20
s.
The IRQ
sweep
pulses are
counted,
see
above,
and
after
50
steps
a
sync
signal
is
sent as
reset signal
to
the
binary
counter 312. This
signal
has
a
duration of
200 ms which
is
equal to the fly-back
time
during
which
setting
to the
start
frequency and
settling
of the
PLL
system
is
achieved.
The
reset
signal,
input
312.7/15
as
the sync
pulse,
is
used
for
master
clear after
power-on.
600
*
t
sweep
Fig.
10
Sweep
frequency
generation
Hide quick links:
Advertisement
Table of Contents
