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11-6
FAIRCHILD ECL
•
11C90
NOTE:
This
diagram
is
provided
for
understanding
of
logic
operation
only.
It
should
not
be used
for
evaluation of
propagation
delays as
many
internal
functions are
achieved
more
efficiently
than shown.
FUNCTIONAL
DESCRIPTION -
The
1
1
C90
contains four
ECL
flip-flops,
an
ECL
to
TTL
converter
and
a Schottky
TTL
output
buffer vvith
an
active pull-up.
Three
of
the
flip-flops
operate as a
synchronous
shift
counter
driving
the fourth
flip-flop
operating as
an asynchronous
toggle.
The
internal
feedback
logic
is
such
that
the
TTL
output
and
the
Q
4 ECL
output are
HIGH
for six
clock periods
and
LOW
for five
clock
periods.
The
Mode
Control (M) inputs
can
modify the feedback
to
make
the output
HIGH
for
five
clock periods
and
LOW
for
five
clock
per-
iods,
as indicated
in
the
Count
Sequence
Table.
The
feedback
logic
is
such
that
at
the
instant
the output
goes HIGH,
the
circuit
is
already
committed
as
to
whether
the output
period
will
be
10
or
1 1
clock periods
long.
This
means
that
subsequent changes
in
an
M
input
signal,
including
decoding
spikes,
will
have
no
effect
on
the
current output
period.
The
only timing
restriction for
an
M
input signal
is
that
it
be
in
the desired
state
at least
a set-up
time
before
the
clock
that
follows the
HHLL
state
shown
in
the
table.
The
allowable propagation delay
through
external
logic to
an
M
input
is
maxi-
mized by designing
it
to
use the
positive transition of
the
1
1
C90
output as
its
active
edge. This gives
an
allowable delay
of ten clock per-
iods,
minus
the
CP
to
Q
delay of
the
1
1
C90
and
the
M
to
CP
set-up
time.
If
the
external
logic
uses
the negative output
transition
as
its
active
edge, the allowable delay
is
reduced
to five
clock periods
minus
the
aforementioned
delay
and
set-up
time.
Capacitively
coupled
triggering
is
simplified
by the
400
0
resistor
which
connects
pin
15
to
the
internal
Vg
0
reference.
By
connecting
this
to
the
CP
input,
as
shown
in
Figure
a.
the
clock
Is
automatically
centered about the
input threshold.
A
clock
duty
cycle of
50%
provides the
fastest
operation, since the
flip-flops
are
master/
slave types
with
offset
clock thresholds
between
master and
slave.
This feature
ensures
that the circuit
will
operate with clock
waveforms
having very
slow
rise
and
fall
times,
and
thus, there
is
no
minimum
frequency
restric-
tion.
Recommended minimum
and
maximum
clock
amplitude as
a function of
a frequency
and
temperature
are
shown
in
the graph
labeled
Figure
e.
When
the
CP
or
any
other input
is
driven
from another
ECL
circuit,
normal
ECL
termination
methods
are
recommended.
One
method
is
indicated
in
Figure
b.
Other
ECL
termination
methods
are
discussed
in
the
Fairchild
ECL
Handbook, Chapters
4
and
5.
When
an
IVI
input
is
to
be
driven
from
a
TTL
output operating
from
the
same
Vqq
and ground
(Vgg),
the
internal
2
k
resistor
can be used
to
pull
the
TTL
output
up
as
shown
in
Figure
c.
Some
types
of
TTL
outputs
will
only
pull
up
to
within
two
diode drops
of
Vqq, which
Is
not
high
enough
for
11C90
inputs.
The
resistor will pull
the
signal
up
through the
threshold
region,
although
this
final rise
may
be
somewhat
slow,
depending on
wiring capacitance.
A
resistor
network
that gives faster
rise
and
also
lower
impedance
is
shown
in
Figure
d.
The ECL
outputs have no pull-down
resistors
and
can
drive series or parallel
terminated transmission
lines.
For short interconnections
that
do
not
require
impedance
matching,
a
270
Cl
to
5100
resistor to
Vgg
can
be used
to
establish
the Vq|_
level.
Both
Vqq
pins
must
always be
used and should be connected
together
as
close
to
the
package as
possible.
Pin
1
2 must always be connected
to
the
Vgg
side
of
the
supply,
white
pin
13
is
required only
if
the
TTL
output
is
used.
Low
impedance
and
Vgg
distribution
and
rf
bypass
capacitors
are
recommend-
ed
to
prevent
crosstalk
with other
circuits.
COUNT SEQUENCE
TABLE
Q<j
Q2
Q3
Q4{QTTL)
Note:
A
HIGH
on
MS
forces
all
Qs
HIGH.
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