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11-8
FAIRCHILD ECL
•
11C90
While
fully
programmable
counters
offer
a
choice
of
9
or
15
different
divide
ratios,
the
fixed
prescaler
offers
only
one
choice.
In
between
these
two
extremes
is
the
variable
mod-
ulus
prescaler,
in
which
a
little
bit
of
speed
is
sacrificed
in
favor
of a
little
freedom
in
choosing
divide
ratios.
A
prescaler
of this
type
plays
a leading
role
in
a pulse
swallowing
count-
er.
An example
is
the
650
MHz
11C90
-r
10/11
prescaler
shown
symbolically
in
Figure
5.
The
1
1C90
contains
three
ECL
flip-flops
operating as
a
syn-
chronous
shift counter,
driving
a
fourth
ECL
flip-flop
operat-
ing
as
an
asynchronous
toggle.
A
shift
counter
is
used because
it
is
the
fastest
configuration
in
the
synchronous menagerie.
As
a
concession
to
speed, there are no preset inputs
and
only
the outputs
of
the
fourth
flip-flop
are
brought
out
of
the pack-
age.
A
third
output
repeats the
Q
waveform
via
an
internal
converter
and a
high
speed
totem-pole
TTL
buffer.
The
intern-
al
feedback logic
is
such
that
the output
is
HIGH
for six
cycles
and
LOW
for
five cycles
of
the input
clock.
An
auxiliary
input
can modify
the
feedback so
that the
output
is
HIGH
for five
cycles
and
LOW
for five cycles. In
either case,
at
the
instant
the output
goes
HIGH,
the
circuit
is
already
committed
as
to
whether
the output
period
will
be
10
or
1 1
clock cycles
long.
Further,
the decision as
to
the length
of
the next
output
period
need
not
be
made
until
just
before the
final
(10th
or 11th)
clock
of
the
current
period.
This feature
means
that
any
ex-
ternal logic
operating
with the
11C90
has almost
10
(or
11)
clock
periods in
which
to
decide
what
the
divide
ratio
of
the
next output
period
will
be
and
apply the appropriate
signal
to
the
auxiliary
control
input.
A
highly
simplified block
diagram
of a
pulse
swallowing
counter
is
shown
in
Figure
6.
The
variable
modulus
prescaler
is
shown
as
two
fixed
prescalers
with
a
switch
to
select
the
output
of
either
one.
A
swallow
counter
controls the position
of
the
switch,
while
a
program
counter provides the
net
out-
put
f
3
,
which
also
serves as
a
Preset
control.
At
the
beginning
of a cycle,
the switch
selects the
upper
prescaler. After
S
pul-
ses
of
swallow
counter throws the switch
to
thelt>wer
prescaler output.
Still
later,
the
program
counter
reacihes
maximum
and causes
a Preset. This
in
turn
causes
the
swa
||ow
counter
to
throw
the switch back
to
the
upper
prescaler
out-
put
and
start
a
new
cycle.
A
slightly
more
sophisticated block
diagram
of
a pulse
swal-
lowing counter
is
shown
in
Figure
7.
The
prescaler
and the
swallow
counter are each
one
stage,
while
the
program
counter
is
normally
two
or
more
stages.
As
a
starting point,
assume
that a
parallel
enable
signal
has
just
occurred
and
the
preset data
has been synchronously
entered
into
ail
the
counter
flip-flops.
This
action returns
the
two TC
outputs
to
the
inactive state,
ending
the Preset
mode. The TC
signal of
the
swallow
counter enables
its
CE
input
and changes
the
prescaler
to
the
upper
(numerically
larger)
divide
ratio.
Both
counters
start
counting
up,
and
after
S
pulses
of
f
2 the
swal-
low
counter reaches
maximum,
its
TC
output
becomes
active,
locking
it
into
the
maximum
state
and
simultaneously
chang-
ing
the prescaler
to
the
lower
divide
ratio.
The
program
count-
er
continues counting up
to
its
maximum, whereupon
its
TC
output
goes
to
the
active state
to
enable the
Preset
mode and
start
a
new
operation
cycle.
It
is
important
to
note
that
the
divide
ratio
M
of
the
program
counter determines
how many
f
2 pulses
there are
in
a
com-
plete
program
cycle;
the
swallow
counter
isn't
involved.
The
role of
the
swallow
counter
is
to
modify, within
limits,
the
number
of
f*|
pulses
into
the prescaler
that
are required
to
produce the
M
pulses
of
f
2
-
n
r e
,
P,;P2 P3
.
MR
<
0_
_
CET
TC
MR
T
BCD DECADE
95016
!
16
BINARY
93S10
B421
BCD DECADE
93S16
MODULO
16
BINARY
Fig.
2.
Examples
of
Programmable
Counters
PROGRAMMABLE DECADES
PRESET
<B-K)
PRESET
(9-M)
r
PARALLEL ENABLE
T
<3 =
<1
/N
I
^
Fig.
3.
Conventional
Programmable
Divider
Ml
MZ
i
ic^:
Fig.
5.
Variable
Modulus
10/11 650
MHz
Prescaier
SWALLOW
(
I
COUNTER
Fig.
4.
Fixed Prescaler
Used
to
Reduce
Frequency
Fig. 6.
Simulated Function
of a
Swallow
Counter
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