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EN 52
8.
3139 785 33120
IC7401 - 4x10bit DigitalVideo Decoder with microvision
BLOCK DIAGRAM
VI_1_A
CVBS/
VI_1_B
Pb/B/C
VI_1_C
VI_2_A
CVBS/
VI_2_B
Y/G
VI_2_C
VI_3_A
CVBS/
VI_3_B
Pr/R/C
VI_3_C
CVBS/Y
VI_4_A
PIN CONFIGURATION
IC Description
Copy
CVBS/Y/G
Protection
Detector
Analog Front End
ADC1
CVBS/Y
C
ADC2
M
U
X
ADC3
ADC4
Sampling
Clock
Timing Processor
with Sync Detector
80
79 78 77 76 75
VI_1_B
1
VI_1_C
2
CH1_A33GND
3
CH1_A33VDD
4
CH2_A33VDD
5
CH2_A33GND
6
VI_2_A
7
VI_2_B
8
VI_2_C
9
CH2_A18GND
10
CH2_A18VDD
11
A18VDD_REF
12
A18GND_REF
13
CH3_A18VDD
14
CH3_A18GND
15
VI_3_A
16
VI_3_B
17
VI_3_C
18
CH3_A33GND
19
CH3_A33VDD
20
21
22 23
24
25 26 27 28
VBI
Data
Slicer
Composite and S-Video Processor
Y/C
Luma
Y
Separation
Processing
5-line
Chroma
C
Adaptive
Processing
Comb
Component
Y/G
Processor
Pb/B
Color
Gain/Offset
Space
Pr/R
Conversion
Figure 8-14
PFP PACKAGE
(TOP VIEW)
74
73
72 71 70
69 68
67 66 65 64
63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
29 30 31 32 33
34 35 36 37 38 39 40
Figure 8-15
YCbCr
Y[9:0]
C[9:0]
Output
Formatter
FSS
YCbCr
GPIO
Host
Interface
C_6/GPIO/RED
C_7/GPIO/GREEN
C_8/GPIO/BLUE
C_9/GPIO/FSO
DGND
DVDD
Y_0
Y_1
Y_2
Y_3
Y_4
IOGND
IOVDD
Y_5
Y_6
Y_7
Y_8
Y_9
DGND
DVDD
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