Table of Contents
Advertisement
QQ
3 7 63 1515 0
ICs BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Pin Function-2
N
. o
P
n i
N
a
m
e
4
1
H
A
9
4
2
G
N
D
4
3
C
D
M
C
K
4
4
C
D
L
R
C
K
4
5
C
D
B
C
K
4
6
C
D
D
A
T
A
4
7
V
D
D
4
8
C
D
D
N I
4
9
N I
T
2
5
0
IN
T
3
5
1
D
R
E
Q
5
2
D
A
C
K
5
3
GI
N
D
5
4
C
L
K
O
5
5
C
L
K
N I
5
6
A
V
D
D
1
5
7
A
G
N
D
1
5
8
A
G
N
D
3
TE
L 13942296513
5
9
A
V
D
D
3
6
0
C
C
A
P
6
1
A
G
N
D
2
6
2
A
V
D
D
2
6
3
A
C
L
K
O
6
4
A
C
L
I K
6
5
H
M
O
D
E
1
6
6
G
N
D
6
7
V
D
D
6
8
A
O
D
6
9
A
O
2
7
0
A
O
1
7
1
A
O
0
7
2
G
N
D
7
3
D
O
U
T
1
7
4
D
O
U
T
0
7
5
S
D
A
7
6
S
C
L
77
VDD
78 GND
8
7
9
DA
C
C
L
K
80
DOCLK
www
8
1
L
R
C
L
K
8
2
H
M
O
D
E
0
.
http://www.xiaoyu163.com
Function
I/
O
P.
n i
I
Ad
d
e r
s s
n i
p
t u
p
o
t r
I
Gr
o
u
n
d
I
Co
n
n
e
t c
o t
g
o r
u
n
d
I
L/
R
c
o l
k c
c
o l
k c
n i
p
u
f t
o r
m
C
D
I
PC
M
b
t i
c
o l
k c
n i
p
u
f t
o r
m
C
D
D
I
Di
g
t i
l a
a
u
d
o i
i
t n
r e
a f
c
e
n i
p
t u
I
Po
w
r e
s
u
p
p
y l
I
PC
M
a
u
d
o i
d
a
a t
n i
p
u
f t
o r
m
C
D
I
t n
r e
u r
t p
e r
q
u
e
t s
s
g i
n
l a
a
g
a
n i
t s
O
e
x
e t
n r
l a
C
P
U
f
o r
m
M
6
5
7
7
3
F
P
O
DM
A
e r
q
u
e
t s
s
g i
n
a
f l
r o
O
S
D
b
D
M
A
a
k c
n
o
w
e l
d
g
e
s
g i
n
a
f l
r o
O
I
t
a r
n
f s
r e
I
Gr
o
u
n
d
O
27
M
H
z
c
o l
k c
o
u
p t
t u
I
Sy
s
e t
m
c
o l
k c
n i
p
t u
I
An
a
o l
g
p
o
w
r e
s
u
p
p
y l
I
A
n
a
o l
g
g
o r
u
n
d
I
An
a
o l
g
p
o
w
r e
s
u
p
p
y l
I
Co
n
n
e
t c
o t
g
o r
u
n
d
I
An
a
o l
g
g
o r
u
n
d
I
An
a
o l
g
p
o
w
r e
s
u
p
p
y l
Op
e
n
I
Au
d
o i
c
o l
k c
n i
p
t u
I
Se
t t
n i
g
p
n i
f o
h
o
s
i t
t n
r e
a f
c
e
o
p
I
Gr
o
u
n
d
I
Po
w
r e
s
u
p
p
y l
O
P
C
M
o
u
p t
t u
f o
a
u
d
o i
d
a
ta
I
Gr
o
u
n
d
D
g i
t i
l a
a
u
d
o i
i
t n
r e
a f
c
e
o
u
p t
ut
O
Open
Open
Power supply
I
Ground
I
Over-sampling operating clock output
O
O
PCM bit clock output
C
o l
k c
o
u
p t
u
f t
r o
i d
c s
i r
m
n i
t a
n i
g
O
x
ao
L (
R /
)
f o
P
C
M
a
u
d
o i
d
a
a t
y
I
Se
t t
n i
g
p
n i
f o
h
o
s
i t
t n
r e
a f
c
e
o
p
i
http://www.xiaoyu163.com
8
N
o
P
n i
N
a
m
e
VDD
D
83
84 VSYNC
HSYNC
85
D
S
P
86
P
C I
S
T
R
S
P
87
M
B
S
T
R
88
M
B
D
A
T
89
GI
ND
D
S
P
90
PWD
91
1
CSYNC
o t
h t
e
92
OSDKEY
t i
m
a
p
t
a r
n
f s
r e
93
X
C
L
S
D
b
t i
m
a
p
94
4
VI
DD
95
P
D7
96
P
D6
97
P
D5
98
P
D4
99
9
GI
ND
100
0
P
D3
Q Q
3
6 7
1 3
101
0
P
D2
102
0
P
D1
103
0
P
D0
104
0
VI
DD
105
0
GI
ND
106
0
RI
E
S
ET
r e
t a
n i
g
m
o
d
e
107
0
T
E
S
T0
108
0
T
E
S
T1
109
0
T
E
S
T2
110
1
0
VI
DD
111
1
N
M
D0
112
1
N
M
D
15
113
1
N
M
D1
114
1
N
M
D
14
11
1
5
GI
ND
116
1
N
M
D2
117
1
N
M
D
13
118
1
N
M
D3
119
1
N
M
D
12
120
2
VI
DD
121
2
N
M
D4
122
2
N
M
D
11
h t
e
c
h
a
n
n
l e
123
2
3
N
M
D5
u163
r e
t a
n i
g
m
o
d
e
124
2
N
M
D
10
.
2 9
9 4
2 8
I/
O
i P
n Function
P
o
w
r e
s
u
p
p
y l
I
V
e
t r
a i
l c
y s
n
. c
s
g i
n
l a
o
utput
O
H
r o
z i
o
t n
l a
y s
n
. c
s
g i
n
a
l output
O
G
o r
u
n
d
I
P
h
a
s
e
c
o
m
p
r a
t a
r o
o
t u
put for external sync.
O
o
p
r e
t a
o i
n
C
o
m
p
o
i s
e t
S
Y
N
C
s
g i
nal input
I
O
S
D
k
e
y
f
a l
g
o
u
p t
t u
O
P
x i
e
c l
o l
k c
2 (
7
M
H
z
r f
ee-running clock)
O
P
o
w
r e
s
u
p
p
y l
I
O
D
g i
t i
l a
p
x i
l e
d
a
ta
G
o r
u
n
d
I
1 5
0 5
8
2 9
9 4
O
D
g i
t i
l a
p
x i
l e
d
a
ta
P
o
w
r e
s
u
p
p
y l
I
G
o r
u
n
d
I
I
H
a
d r
w
a
e r
e r
s
t e
n i
p
t u
I
C
o
n
n
e
t c
o t
g
o r
u
n
d normally
P
o
w
r e
s
u
p
p
y l
I
I/
O
Data transfer line with DRAM
G
o r
u
n
d
I
I/
O
D
a
a t
t
a r
n
f s
r e
n i l
e with DRAM
I
P
o
w
r e
s
u
p
p
y l
m
I
/
O
D
a
a t
t
a r
n
s
e f
r line with DRAM
co
DV-SP500
9 9
2 8
9 9
Advertisement
Table of Contents
