Denon DCD-510AE Service Manual page 27

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Pin
Symbol
No.
26 DVSS3
Ro
27
DVDD3
28
DVR
29
Lo
30
DVSS3
31
VDDT3
32
VSS
33
VDD1
34
VDDM1
35
SRAMSTB
36
/RST
37
BUS0
38
BUS1
39
BUS2(So)
40
BUS3(Si)
41
TE
BUCK(CLK)
L 13942296513
42
/CCE
43
TEST
44
IRQ
45
AoUT3(Po4)
46
AoUT2(Po5)
47
Pio0
48
Pio1
49
Pio2
50
Pio3
51
VSS
52
VDDT3
53
SBSY
54
SBOK
55
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I/O Description
Grounding pin for 3.3V DAC circuit
O
R channel audio output pin of Audio DAC.
3AI/F
Power supply pin for 3.3V Audio DAC
circuit.
Reference voltage pin for Audio DAC.
O
L channel audio output pin of Audio DAC
3AI/F
Grounding pin for 3.3V Audio DAC circuit
Power supply pin for 3.3 V digital I/O circuit.
Grounding pin for 3.3V digital circuit
Power supply pin for 1.5V digital circuit.
Power supply pin for 1.5V 1Mbit SRAM.
I
1Mbit SRAM stand-by pin
3I/F
I
Reset signal input pin.
3I/F
IO Data input/output pin -0 for
microcontroller interface
3I/F
IO Data input/output pin -1 for
microcontroller interface
3I/F
IO Data input/output pin -2 for
microcontroller interface (Serial output)
3I/F
IO Data input/output pin -3 for
microcontroller interface (Serial input)
3I/F
Clock input pin for the microcontroller
I
interface. (Clock input for Serial
3I/F
communication interface)
I Chip enable signal input pin for
microcontroller interface.
3I/F
I Setting pin for LSI test mode.
(Connect to GND in normal operation)
3I/F
I
DSP interruption pin.(Pull down by 100k
when not in use)
3I/F
O Audio data output pin -3 (DSP general
output port -4)
3I/F
O Audio data output pin -2 (DSP general
output port -5)
3I/F
I/O
DSP general input/output port -0
3I/F
I/O
DSP general input/output port -1
3I/F
I/O
DSP general input/output port -2
3I/F
I/O
DSP general input/output port -3
3I/F
Grounding pin for 3.3V digital circuit
Power supply pin for 3.3 V digital I/O circuit.
O
Sub code block sync output pin
3I/F
O CRCC check result output pin for sub code
Q data.
3I/F
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8
Q Q
3 6 7 1 3
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27
DCD-510AE
9 4 2 8
Default
Remarks
O
No capacitor required to
DVR pin when built-in
audio DAC is not in use,
however , connect 3.3V to
DVDD3 and GND to
O
DVSS3.
-
-
-
I Schmitt input
I Schmitt input
Schmitt input
I
CMOS PORT
Schmitt input
I
CMOS PORT
Schmitt input
I
CMOS PORT
Schmitt input
I
CMOS PORT
I Schmitt input
1 5 0 5 8 2 9 9 4
I Schmitt input
I Schmitt input
I Schmitt input
O CMOS PORT
O CMOS PORT
Schmitt input
I
CMOS PORT
Schmitt input
I
CMOS PORT
Schmitt input
I
CMOS PORT
Schmitt input
I
CMOS PORT
-
-
O CMOS PORT
O CMOS PORT
m
co
9 9
2 8 9 9