Yamaha AV-S70 Service Manual page 32

A B
AV-S70/NX-SW70
AV-S70 SCHEMATIC DIAGRAM (2/4)
1 Q Q
3 7 6 3 1 5 1 5 0
2.9
DIGITAL 2
2.4 2.9
0
4.7
0
2
DIGITAL 1 0 4.7
0 4.7 0
PLL CONT
4.7
0
3
4.7
0
0 0
4
0
0 0
0 0
DIR
0 0
4.7
4.7 T E 0
L q 1 3 9 4 2 2 9 6 5 1 3
4.7
4.7
0
2.3
4.8 2.2
5 2.3
2.3
6
7
w w w
PIN CONNECTION DIAGRAM OF TRANSISTORS, DIODES AND ICS.
8 µPC29M33T
1SS355 2SC3326 (B) M5220FP
DTA143EKA NJM2904M
4
Anode
1 2
3
C
5
E 8
1: INPUT
B
Cathode 2: GND
3: OUTPUT
1
4: GND
37
C D E
0.3
0
0 0
0
4.7
2.3
2.3
1.4
0
2.2
2.2
~
4.6
0
3.2
0
0
0
AC3Dav
0
0
0
0
0
0
2.3
RAM
P-38
D-6
x a o
HD74HC02FPEL LP61256GS-8 CS4227-KQ YSS908-F
YM3436
. i
80
15 33 23
81
34 22
8
14
28
14
7
4 12
44
1
1 100
1 11
1
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P-38
F-6
0.1
0
4.7
0.1
0.1
2.1
4.7
4.7
0
0 0
0
C823
0 560p
2.3
2.3
0
0
0
0
2.3
2.3
2.3
2.3
0
2.3 1.4
4.7
3.2 2.3
2.3
0 2.3
0
C824
2.3
4.4
560p
0
DAC/ADC
4.6
0 2.3
0
0
4.6
2.3
0
4.6
C825
560p
Q Q
3 7
3.3 4.7
0
2.3
2.3
22.9
–22.7
2.3
2.3
Point q (Pin 13 of IC3)
u 1 6 3
y
V : 2V/div, H : 0.1 µsec/div
DC, 1 : 1 probe
51
50
0V
31
30
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H I
2 4
8 9
MAIN L
0
0
22.9
0
0
0
0
0
22.9 C821 560p
–22.7
0
–0.1
0
0
6 3 1 5 –0.1 1 5 0 8
0
22.9
–22.7
0
–0.1
0
2.3
2.3
22.9
–22.7
2.3
2.3
IC2 : HD74HC02FPEL
Quad 2 Input NOR
m
IC1 : NJM2904M
IC8~12 : M5220FP
Dual OP Amp
c o
14 13 12 11 10 9 8
.
OUT 1 1 8 +V CC
–IN 1 2 7 OUT 2
+ – + –
+IN 3 6 –IN
1 2
1 2 3 4 5 6 7
–V 4 5 +IN
CC 2
J K
IC6 : CS4227-KP
AD Converter/DA Converter
2
9 8 9 9
44 43 42 41 40 39 38 37 36 35 34
DATAUX 1 33 SDIN2
HOLD SDIN3
2 32
SCL/CCLK 3 31 CLKOUT
SDA/CDOUT 4 30 OVL
AD1/CDIN 5 29 XTO
AD0/CS 6 28 XTI
SPI/I2C 7 27 DEM
PDN 8 26 AOUT6
AIN3R AOUT5
9 25
AIN3L 10 24 AOUT4
AIN2L 11 23 AOUT3
12 13 14 15 16 17 18 19 20 21 22
3 4 5 6 7 40 19
VOLTAGE
PDN 8 CONTROL PORT 16 CMOUT
REFERENCE
DAC#1
VOLUME
LRCK 37
CONTROL
21 AOUT1
DAC#2 VOLUME
SCLK 38
CONTROL 22 AOUT2
SDIN1 34 DAC#3
VOLUME
23 AOUT3
CONTROL
SDIN2 33
DAC#4 VOLUME
24 AOUT4
CONTROL
SDIN3
32
DAC#5
VOLUME 25 AOUT5
CONTROL
SDOUT1 36
26 AOUT6
DAC#6 VOLUME
SDOUT2 35 CONTROL
MONO
15 AINAUX
ADC
OVL
30 LEFT 14 AIN1L
MUX
INPUT
ADC
GAIN 13 AIN1R
RIGHT
12 AIN2R
ADC
11 AIN2L
DEM 27 DEM
10 AIN3L
CLOCK OSC/
AGND1 AUXILIARY INPUT 9 AIN3R
18 DIVIDER
LFE
20 31 28 29 2 1 44 43 41 39
P-36
D-1
IC7 : LP61256GS-8
32K X 8 bits High Speed Static RAM
REAR L
A14 1 28 VCC
A12 2 27 WE
A7 3 26 A13
A6 4 25 A8
A5 5 24 A9
A4 6 23 A11
9 2 4 9 8 2 9 9
A3 7 22 OE
A2 8 21 A10
A1 9 20 CE
A0 10 19 I/O8
I/O1 11 18 I/O7
I/O2 12 17 I/O6
I/O3 13 16 I/O5
GND 14 15 I/O4
A0 VCC
A5
MAIN L GND
A7 ROM 256 x 1024
DECODER MEMORY ARRAY
A9
A12
I/O1
COLUMN I/O
INPUT
DATA
CIRCUIT
I/O8
COLUMN DECODER
A1 A14
CE
CONTROL
OE
CIRCUIT
WE
IC801 : TC74HCUO4AF IC802 : TC74HC153AF
Hex Inverters Dual 4 to 1 Data Selectors
STROBE A DATA INPUTS OUTPUT
VCC 2G SELECT 2Y
1A 1 14 V 16 15 14 13 12 11 10 9
DD
1Y 2 13 6A 2C3 2C2 2C1 2C0 2Y
2G
B B A A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
B B A A
3Y 6 9 4A 1G
1C3 1C2 1C1 1C0 1Y
V SS 7 8 4Y
1 2 3 4 5 6 7 8
STROBE B OUTPUT GND
DATA INPUTS
1G SELECT 1Y
INPUTS OUTPUT
SELECT STROBE
Y
B A G
X X H L
L L L C0
L H L C1
H L
L C2
H H L C3
* All voltage are measured with a 10MΩ/V DC electric volt meter.
* Components having special characteristics are marked Z and
must be replaced with parts having specifications equal to those
originally installed.
* Schematic diagram is subject to change without notice.
L