Sharp LC-42SB45U Service Manual page 51

3.3. U104/U103 (L5985 VFQFPN8)
3.3.1 Pin Connections and short description
Type Description
N°
OUT Regulator output
1
SYNCH Master/Slave Synchronization. When it is left floating, a signal with a phase shift of half a period respect to the power turn
2
on is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the
device is synchronized by the external signal, with zero phase shift.
Connecting together the SYNC pin of two devices, the one with higher frequency works as master and the other one as
slave; so the two power turn on have a phase shift of half a period.
INH A logical signal (active high) disable the device. With INH higher than 1.9V the device is OFF and with INH lower than
3
0.6V the device is ON.
COMP Error Amplifier output to be used for loop frequency compensation
4
FB Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6V. To have higher
5
regulated voltages an external resistor divider is required from Vout to FB pin.
F The switching frequency can be increased connecting an external resistor from FSW pin and ground. If this pin is left
6
SW
floating the deice works at its free-running frequency of 250KHz.
GND Ground
7
V Unregulated DC input voltage
8
CC
3.4. U351/U352 (HYB18TC256160BF-3S TFBGA-84-55)
3.4.1 Pin Connections and short description
Ball#/Pin# Name
Data Signals ×16 Organization
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1 DQ4
H9 DQ5
F1 DQ6
F9 DQ7
C8 DQ8
C2 DQ9
D7 DQ10
D3 DQ11
D1 DQ12
D9 DQ13
B1 DQ14
B9 DQ15
Data Strobe ×16 Organization
B7 UDQS
A8
UDQS
F7
LDQS
Pin Type Buffer Type
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
2008-03-14
I/O SSTL
I/O SSTL
I/O SSTL
Function
Data Signal 15:0
Data Strobe Upper Byte
Data Strobe Lower Byte
51
LC-42SB45U