operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current

and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996 also incorporates a V

pin to provide superior

SENSE

load regulation and a V

output as a reference for the chipset and DIMMs. An additional feature found on the LP2996 is an active low shutdown (SD) pin

REF

that provides Suspend To RAM (STR) functionality. When SD is pulled low the V

output will tri-state providing a high impedance output, but, V

will

REF

remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

Features

· Source and sink current

· Low output voltage offset

· No external resistors required

· Linear topology

· Suspend to Ram (STR) functionality

· Low external component count

· Thermal Shutdown

· Available in SO-8, PSOP-8 or LLP-16 packages

Applications

· DDR-I and DDR-II Termination Voltage

· SSTL-2 and SSTL-3 Termination

· HSTL Termination

23.U103/ U104 (L5985 VFQFPN8)

Description

The L5985 is a step down switching regulator with 2.5A current limited embedded power MOSFET, so it is able to deliver up to 2A DC current to the load

depending on the application condition.

The input voltage can range from 2.9V to 18V, while the output voltage can be set starting from 0.6V to V

. Having a minimum input voltage of 2.9V, the

device is suitable for buses staring from for 3.3V bus.

Requiring a minimum set of external components, the device includes an internal 250KHz switching frequency oscillator that can be externally adjusted up

to 1MHz.

The QFN package with exposed pad allows reducing the R

down to approximately 60°C/W.

thJA

Features

· 2A DC output current

· 2.9V to 18V input voltage

· Output voltage adjustable from 0.6V

· 250KHz switching frequency, programmable up to 1MHz

·Internal Soft-start and Inhibit

· Low dropout operation: 100% duty cycle

· Voltage feed-forward

· Zero load current operation

· Over current and thermal protection

· VQFN3x3-8L package

Applications

· Consumer:

STB, DVD, DVD recorder, car audio, LCD TV and monitors

· Industrial:

Chargers, car battery, PLD, PLA, FPGA

· Networking: XDSL, modems, DC-DC modules

· Computer:

Optical storage, hard disk drive, printers, audio/graphic cards

2.4. U351/U352 (HYB18TC256160BF-3S TFBGA-84-55)

Features

The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

· 1.8 V ± 0.1 V Power Supply

· 1.8 V ± 0.1 V (SSTL_18) compatible I/O

· DRAM organizations with 4, 8 and 16 data in/outputs

· Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation

· Programmable CAS Latency: 3, 4, 5 and 6

· Programmable Burst Length: 4 and 8

· Differential clock inputs (CK and CK)

· Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write

data.

· DLL aligns DQ and DQS transitions with clock

· DQS can be disabled for single-ended data strobe operation

Table of Contents