Sony PCM-D50 Service Manual page 58

PCM-D50
Pin No. Pin Name
W4, W5 SDR_A4, SDR_A3
W8 SPI1_SO
W9 GND
W10 SPI1_CSZ0
W11 to W18 GND
W19 EXTPCMCLK
W22 D_TDI
W23 C_TDI
W24, W25 IO_B
W26 VLO
Y1 IOVDD
Y2 GPIO13
Y3 GPIO12
Y4, Y5 SDR_A2, SDR_A1
Y22, Y23 TM1, TM0
Y24, Y25 VDD_DSP
Y26 VHP
AA1 GPIO12
AA2 GPIO10
AA3 GPIO9
AA4 SDR_A0
AA5 SDR_CLK
AA22, AA23 TMC2, TMG
AA24 TM2
AA25 VANAIN
AA26 VANA
AB1 VDD_L0
AB2 GPIO8
AB3 GPIO7
AB4 GPIO6
AB5 SDR_BA0
AB6 SPI0_CSZ1
AB7 SPI0_SI
AB8 SPI1_SI
AB9 IO_C
AB10 CAM_YUV7
AB11 CAM_YUV4
AB12 CAM_CLK
AB13 CAM_STR
AB14 CAM_SCLK
AB15 to MS_DATA3, MS_DATA2,
AB17 MS_DATA0
AB18 MS_INSZ
AB19 EXTCLK
AB20 PM1_SEN
AB21 PM1_CLK
AB22 PM0_SEN
AB23, AB24 TCM1, TM3
AB25 GND1
AB26 OSCIN
AC1 to AC3 IO_A
AC4 GPIO5
AC5 GPIO4
AC6 SPI0_CSZ0
AC7 SPI0_SK
AC8 SPI0_SO
58
I/O
O Address signal output to SD-RAM
O Serial data output to the digital audio I/F transceiver
— Ground
O Chip select signal output to the digital audio I/F transceiver
— Ground
I MCLK clock input
O CD signal output to the LCD unit
— Not used (Open)
— Power supply (VDD_GP1)
O VDD_L0 power supply output
— Power supply (VDD_GP1)
I Headphone connection detection signal input
I POWER (S2002) switch off signal input
O Address signal output to SD-RAM
I Not used (Pull up)
— Power supply (VDD_L1)
— Not used (Open)
I SIRCS detect signal input
I LOW CUT FILTER (S1602) switch signal input
I LIMITER (S1601) switch signal input
O Address signal output to SD-RAM
O Clock signal output to SD-RAM
— Not used (Connected ground)
I Not used (Pull up)
— Power supply (+3.3V)
O VDD_ANA power supply output
— Power supply (VDD_L0)
I DPC (S2213) switch signal input
I USB interrupt signal input
I LINE IN connection detection signal input
O Bank address signal output to SD-RAM
— Not used (Connected ground)
I Not used (Open)
I Serial data input from the digital audio I/F transceiver
— Power supply (VDD_GP1)
O MIC/LINE IN power supply control signal output
O Power supply control signal output
O LINE IN (OPT) receiver power control signal output
O 24.575MHz clock generator control signal output
O DIV clock control signal output
I/O MS data input/output
I Read/busy signal input
— Not used (Open)
O L/R sampling clock signal output to the D/A converter
O Serial clock signal output to the D/A converter
O L/R sampling clock signal output to the D/A converter
— Not used (Connected ground)
— Ground
I Sub system clock input (32.768kHz)
— Power supply (VDD_IOA)
I LINE IN (OPT) connection detection signal input
I LINE OUT connection detection signal input
O Chip select signal output to the LCD unit
O Serial data transfer clock signal output to the D/A converter
O Serial date output to the LCD unit
Description