Block Diagram - Ad Section - Sony PCM-D50 Service Manual

PCM-D50
4-1. BLOCK DIAGRAM – AD Section –
Q3001
MIC001
(L-CH)
MIC002
(R-CH)
J3001
Q3009
Q3008
R-CH
J3002
LINE IN
(OPT)
VOUT
VCC
Q3005
+D2.85VCC
PCM-D50
MIC BIAS
Q3002
S3002
INPUT
MIC AMP
IC3001
LINE
3
1
2
R-CH
S3003
MIC ATT
20
RV003
0 REC LEVEL
S3002 (2/2)
S1601 S1602
LIMITER LOW CUT
FILTER
ON
OFF
OFF
ON
LINE AMP
IC3003
5 7
R-CH
LINE AMP LINE AMP
S3002 (1/2)
IC3002 IC3004
5 7 5 7
R-CH
POWER
DVCC_CONT
E
SECTION
(Page 22)
42
S4202 S4201
MIC (L-CH) MIC (R-CH)
DIRECTION DIRECTION
SYSTEM CONTROL/DSP
IC1001 (1/3)
20 20
A/D CONVERTER
IC3005
2 AINL SDTO 6 3
1
BCK 12
1 AINR LRCK 10
MCLK
11
AD1_XRST
PDN 13
A/D CONVERTER
IC3006
AINL SDTO
2 6 3
1
BCK 12
1 AINR LRCK
10
MCLK 11
AD2_XRST
PDN
13
4
DIGITAL AUDIO
I/F TRANSCEIVER
IC3404
BICK 26
LRCK
24
DAUX 28
SDTO 25
UOUT
19
MCLK01 23
RX0
XT1 30
TX1
16
DIF_INT
INT0 36
DIF_XCS
OCKS0/CSN/CAD0
35
SPT1_CLK
OCKS1/CCLK/SCL 34
SPT1_MOSI
CM1/CDTI/SDA 33
SPT1_MISO X11M_CONT
CM0/CDTO/CAD1
32
DIF_XRST
PDN 31
X24M_CONT
DIV24M_CONT
X1401 X1101
32.768KHz 12MHz
DATA SELECT
IC3406
PCM0_ADDT
4
6
DATA SELECT
IC3407
PCM1_ADDT DA
A
4
SECTION
(Page 21)
6
CLOCK SELECT
IC3405
PCM_MCLK
3
1
6
PCM0_BCK
PCM0_LRCK
PCM0_DADT
SDTO1_XAD1
OPT_OUT DA
B
SECTION
(Page 21)
CLOCK GENERATOR
IC3401
1 FOUT XXT 3
X3401
11.2896MHz
4 CONT XT 5
CLOCK GENERATOR
IC3403
6 FOUT XT 2
X3402
24.576MHz
1 CONT XT– 3
7 IN1
• R-ch is omitted due to same as L-ch.
• SIGNAL PATH
: PB (DIGITAL)
: REC (ANALOG)
: REC (DIGITAL)