System Control Block Diagram - Sony DVP-S335 Service Manual

DVP-S335/S336/S345/S535D/S735D
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3-4. SYSTEM CONTROL BLOCK DIAGRAM

MB-86 BOARD (3/6)
(SEE PAGE 4-25 to 4-32)
HD 8 – 15
RF/SERVO
(SEE PAGE 3-4)
HA 0, 1
HA 0 – 21
HD 0 – 15
RD
WRH
SIGNAL PROCESSOR
(SEE PAGE 3-5)
ARPRST
ARINT
XARPCS
ARPWT
AVWT
XDRV MUTE
T E
SDSPINT
L 1 3 9 4 2 2 9 6 5 1 3
RF/SERVO
XSDSPCS
(SEE PAGE 3-4)
CKSW1
OCSW1
OCSW2
WIDE
EUROVY
VIDEO/AUDIO (2) RGBSEL
(SEE PAGE 3-11)
FS
DISCEXT
YUVRGB
DREQ0
DACK0
DREQ1
DACK1
IC1054
XAVDCS2
XAVDCS3
AVINT
5.2 Vp-p (27 MHz)
CD DOUT
SIGNAL PROCESSOR
(SEE PAGE 3-5, 6)
IC105 qh
27MAVD
DVD: 4.3 Vp-p (29.5 MHz)
CD: 4.3 Vp-p (22.58 MHz)
512FSAVD
IC105 qs
33MARP
w w w
33MAVD
4.9 Vp-p (33.8688 MHz)
RF/SERVO
27MSDP
(SEE PAGE 3-4)
05
IC104
FLASH
HD 8 – 15
HA 0, 1
HA 0 – 21 HA 0 – 21
HD 0 – 15
HD 0 – 15
1 – 5 102 – 109 111 – 118 120 85 – 100 65
CSOX
RD
WRH
INT2
CS5X
IC102 ua
CPUCK
XRST
4 Vp-p (25.3 MHz)
INT3
22 ARPRST
26 INT1 ECS
69 CS4X EWC
79 XWAIT SO0
SI0
IC102
SCO
SYSTEM
CONTROL
23 DRV MUTE
32 INT7
18 CS6
56 CKSW1
57 OCSW1 IFCS
58 OCSW2 INT4
FRRST IN
A
AURST
63 WIDE DACCS1
20 EUROV/Y DACCS0
7 GAIN/RGBSEL MAMUTE
8 DACMUTE/FS
IC102 tf
21 CLAPSWO/DISCEXT
42 YUVRGB/CLAPSW1
CKSW2
43 CLAPBSY
DREQ0
SC1
44 DACK0 2.4 Vp-p (12.5 MHz)
SO1
46 DREQ1
47 DACK1 KCS/39CS
67 CS2X SI1
68 CS3X
25 INTO
61 53 54
X101
12.5MHz
IC105
PLL
4 27M2
44.1/48k
23 44.1/48k
512FS2
16 512FS1
12 33M
IC105 8,9
27M3
IN OUT
8 9
x a o
X102
2.5 Vp-p (27 MHz)
27MHz
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RD
WRH
1 – 5
SHA0 – 3 19
82 11 RDN
83 10 WRN
FGAINT
27 12 INT
XFGACS
70 48 CS5
CPUCK
71 8 CK
XRST
16 9 XRST
28 1 R/B
49 3 CS
48 8 WC
IC101
35 5 DI
B+
33 6 DO
EEPROM
(3.3V)
36 4 SK
SC0
Q Q
3 7
SI0
SO0
XIFCS
45
IFBSY
29
XFRRST
74
AURST
51
6CH/VES CS
60
2CH CS
59
MAMUTE
62
A
39INT
30 107 CMD ACKNO
CMDREQ
31 108 CMD REQNO
SC1
39 115 SH CLKI
SO1
38 117 SH SII
KCS/39CS
50 118 SH CSNI
SI1
37 119 SH SOO
IC105 qg
IC701
AUDIO
DSP
DVD: 3.4 Vp-p (29.5 MHz)
CD: 3.4 Vp-p (22.58 MHz)
10 DSP1DII
32 DSP2DII
S535D/S735D
512FS6CH
512FS2CH/VES
512FS39
15 8 DSP1DIACKI
34 DSP2DIACKI
67 DSP2ACKI
149 DSPIACKI
27M39
24 22 SCLKI
IC105 wf 6 RESET NI
u 1 6 3
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4.9 Vp-p (27.2 MHz)
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2 4
8 9 9
IC802
NAND FLASH
15 – 18
D0 – 3
13
20 TEST, CLE, ALE, XWE,
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IC801 XWP, XCE, XRE, R/B
24
26
FGA
37
S735D
XRST
512FS6CH
B
512FS2CH/VES
IC103
SC1
5 4
RESET SO1
SI1
SC0
6 3 1 5 1 5 0 8 9
SI0
SO0
XIFCS
XIFBUSY
XFRRST
AURST
6CH/VES CS
2CH CS
MA MUTE
6CH FRONT
DSP2 CH12O 48
6CH REAR
DSP2 CH34O 49
KCS/6CH C/SW
DSP2 CH56O 50
LRCK
DSP2 LRCKO 42
BCK
DSP2 BCKO 43
S335/S336/S345
6CH FRONT
DSP2 CH12I 56
6CH REAR
DSP2 CH34I 57
6CH C/SW
DSP2 CH56I 58
DSP2 LRCKI 55
DSP2 BCKI 69
2CH DATA
DSP2 CH78O 51
DSP2 DO 45
S335/S336/S345
DSP1 CH12I 160
DSP1 CH34I 159
DSP1 CH56I 158
DSP1 LRCKI 161
DSP1 BCKI 147
TDO 139
TDI 140
TMS 141
m
TCK 143
TRST 142
c o
B
.
S535D/S735D
3-8
2
8 9 9
SIGNAL PROCESSOR
XRST
(SEE PAGE 3-5)
RF/SERVO
XRST
(SEE PAGE 3-4)
512 FS 6CH
512 FS 2CH/VES
AUDIO (1)
SC1
(SEE PAGE 3-9)
SO1
SI1
SC0
2 4 9 8 2 9 9
SI0
INTERFACE
SO0
CONTROL
XIFCS
(SEE PAGE 3-13)
XIFBUSY
XFRRST
AURST
6CH/VES CS
2CH CS
MA MUTE
6CH FRONT
6CH REAR
KCS/6CH C/SW AUDIO (1)
(SEE PAGE 3-9)
6CH LRCK
6CH BCK
BCK
6CH FRONT
6CH REAR
6CH C/SW
LRCK
LRCK
BCK
BCK
2CH DATA
SPDIF INTERFACE
SPDIF
CONTROL
(SEE PAGE 3-13)
SPDIF1
ACH12
ACH34
ACH56
LRCK
SIGNAL PROCESSOR
BCK
(SEE PAGE 3-6)
TDO39
TDI32
TMS
TCK
TRST