Pioneer AVH-P6400CD UC Service Manual page 110

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QQ
3 7 63 1515 0
*TC90A64AF
A
1
DRAM Vss
Vss
2
Gate Scan Start 1
3
Gate Scan Start 2
4
Gate Clock Out
5
Gate Enable Out
6
DRAM VDD (DR.2.5V)
VDD
7
Signal Polality Out
H.Sampling Clock
8
Output Signal Clamp Pulse 9
Digtal Vss 10
Vss
VCO Monitor
VCO Moniter 11
Digital VDD(2.5V) 12
VDD
13
H.Sampling Latch Select
14
H.Sampling Start1
H.Sampling Start2 15
Digital VSS 16
Vss
D.RAM Test 17
HD1
18
H.Sync IN
VD1
V.Sync IN 19
B
C.Sync1
RGB 2 C.V.Sync IN
20
CKP
21
Ext.PLL Clock
HREF
Ext.PLL H.ref.
22
CKPSEL
Ext.PLL Select 23
Buffer VDD(3.3V) 24
VDD
25
Buffer Vss
Vss
Analog Vss 26
Vss
POLC
D/A Bias 1 27
D/A
Common Polality Out 28
29 VDD
Analog VDD(2.5V)
TE
L 13942296513
30 D/A
Ext.Clamp Bias Out
D/A Bias Out 31
REFO
Analog Vss 32
Vss
Analog VDD(2.5V) 33
VDD
Red
R Signal Out 34
Green
D/A Bias 3 35
36
G Signal Out
C
MAX1748EUE
rdy 1
OSC
FB 2
3
INTG
IN 4
GND 5
www 6
REF
D
FBP 7
FBN 8
110
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144 143 1 42 141 140 139 138 137 136 135 134 133 132 131 130
Vss VDD
NGOE
STV1
STV2
CPV
Control
NDSV
POLS
CPH SCKE
CLMPO NDSH
VCOM
STH1
STH2
CX
OSD
Cont./Bright
γ Process
Signal
Polarity
HD2
Main Timing
VD2
Pulse Gene
1 / 3050
Mute
H/V Sep
1 / 3048
10bit
1/ 2 4. 8 M
D/A
PD1/PD2 1/ 5
9. 6 M
CP1/CP2
1/ 6
8. 0 M
D/A
Analog
PLL VCO
D/A
48M
Blue
VDD Vss VDD VDD AGS1 Vss VDD
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
S
R
Q
-
I
LIM
+
+
+
-
-
Gm
x ao
+
y
+ -
-
. i
1.25V
AVH-P6400CD/UC
2
http://www.xiaoyu163.com
3
8
129 128 127 126 125 124 123 122 121 120 119 118 117 116 115
VD D Vss
2M
Memory
R
Output RGB PIP
G
Switch Matrix Process
B
C.Video
Cont./Bright
Y U V
Color
Decode
C
C.Video
Side
NTSC:2line
Y/C Sep
RGB
PAL:LPF/BPF
Side
8bit
A/D A/D A/D
Q Q
3 6 7
A/D 8bit
Ped.Clamp(63.5LSB)
R G B
13. 5 M
27M
Ped.Clamp
(8LSB)
Ped.Clamp
(8LSB)
Vss VDD VDD Vss
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
TK15404MI
16 TGND
VREF 1
15 LX
14 PGND
OUT 2
13 SUPP
12
DRVP
IN- 3
11
SUPN
u163
10
DRVN
9 shdn
3
4
2 9 9 4
1 1 4 113 112 111 1 10 109
108 DRAM Vss
Vss
107
Test mode3
106 Test mode2
105 Dispaly Mute
104 Reset IN
ACK 103
VDD DRAM VDD(DR.2.5V)
102
OSD H.Sync Out
101 OSD Clock Out
100
OSD V.Sync Out
99
Bus Data I/O
Bus
98 Digital VDD(2.5V)
VDD
Inter
97 Test mode1
Face
96
Bus Serial Clock IN
95
Test mode0
FNAVI
94
Digital Vss
Vss
93 RGB Over lay Cont.IN
OSD
Side
92
OSD Blank IN
OSD
91
OSD B IN
Color
Inter
90 OSD G IN
Palette
Face
89 OSD R IN
88
C.Video Sync IN
C.Sync2
87 C.Video Signal IN1 Cl amp Out1
86
C.Video Signal IN2 Cl amp Out1
85
Digital VDD(2.5V)
VDD
84
Buffer VDD(3.5V)
VDD
XO
Sub Timing
83 X'tal IN
42 M
Pulse Gene
82 X'tal OUT
HD2
81
Vss Buffer Vss
Digtal
VD2
PLL
80
Sub PLL Digital Vss
Vss
H/V Sep
1 3 1 5 0 5 8 2 9
79 Sub PLL Analog Vss
Vss
D/A
1/ 2
78 A.G.S.2
AGS
VCO
1/ 2
77 Sub PLL Filter
54M
Sub PLL Analog VDD(2.5V)
76
VDD
PC1,CP1
1/ 4
75 Sub PLL Digital VDD(2.5V)
VDD
x 4 74 Sub PLL IN
Li m
Analog
PLL 73
VDD CK D/A Analog VDD(2.5V)
Vss
67 68 69 70 71 72
Reference
Standby Logic
+
-
m
co
.
4
2 8
9 9
9 4 2 8 9 9
6
VCC
5
GND
4
IN+