Pioneer DV-565A-S Service Manual page 82

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QQ
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A
¶ Block Diagram
2 UARTs,
2
2 I C-SSCs,
IR transceiver
MAFE interface
B
DVD
Programmable
CPU interface
(EMI)
Ext peripherals:
flash, additional
C
DRAM SDRAM
TE
L 13942296513
16, 32, 64 or
128-Mbit
SDRAM
Analog/digital
D
Video output,
480i/480p
E
www
F
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Internal peripherals
Central
command port
Low power
mode
DMAs
Front-end &
link interface
DMA
Communications
arbiter
I/F
Shared
SDRAM
interface (SMI)
OSD, SP
DENC decoder
and mixing
x ao
. i
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CPU
(C2+)
Clock
generator
ST20 arbiter and memory controller
SDRAM
CD FIFOs
block move
Q Q
3 6 7
SDRAM arbiter (LMC)
Audio &
Video
Video
Karaoke
filtering decoder
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DV-565A-S
3
2 9 9 4
8
Cache sub-system
RID TAP
ICache
SRAM
Refill
control
DCache
Diagnostic
controller
JTAG
debugging
CPU arbiter interface
Command I/F
1 3 1 5 0 5 8 2 9
Audio
in/out
m
co
.
4
2 8
9 9
9 4 2 8 9 9
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