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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-12
Q301 : CS42518 (8-ch Codec with S/PDIF Receiver)-1/4
BLOCK DIAGRAM
RXP0
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
MUTEC
FILT+
VQ
REFGND
VA
AGND
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
TE
L 13942296513
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
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TXP
VARX
AGND
LPFLT
Clock/Data
Rx
Recovery
GPO
MUTE
Ref
ADC#1
Digital Filter
ADC#2
Digital Filter
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
DAC#7
DAC#8
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8
DGND DGND VD
C&U Bit
Data Buffer
S/P DIF
Decoder
Format
Detector
Internal MCLK
DEM
Gain & Chip
ADC
Serial
Data
Gain & Chip
Q Q
3
6 7
1 3
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TX-SR504/504E/8450
2 9
9 4
2 8
VD
Control
Port
Mult/Div
Serial
Audio
Interface
Port
1 5
0 5
8
2 9
9 4
CODEC
Serial
Port
m
co
9 9
INT
RST
AD0/CS
AD1/CDIN
SDA/CDOUT
SCL/CCLK
VLC
OMCK
RMCK
SAI_LRCK
SAI_SCLK
SAI_SDOUT
VLS
ADCIN1
ADCIN2
CX_SDOUT
CX_LRCK
2 8
9 9
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
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