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3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-6
Q201 : D707E001RFP250 (32 bit Floating-Point Digital Signal Processor)-6/7
TERMINAL DESCRIPTION (3/4)
SIGNAL NAME
AHCLKR0/AHCLKR1
ACLKR0
AFSR0
AHCLKX0/AHCLKX2
ACLKX0
AFSX0
AMUTE0
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
AXR0[4]
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
TE
L 13942296513
AXR0[8]/AXR1[5]/
SPI1_SOMI
AXR0[9]/AXR1[4]/
SPI1_SIMO
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR1
AFSR1
AHCLKX1
ACLKX1
AFSX1
AMUTE1
SPI0_SOMI/I2C0_SDA
SPI0_SIMO
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
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PIN
TYPE
NO.
McASP0, McASP1, McASP2, and SPI1 Serial Ports
143
IO
139
IO
141
IO
2
IO
142
IO
144
IO
3
O
113
IO
115
IO
116
IO
117
IO
119
IO
120
IO
121
IO
122
IO
126
IO
127
IO
130
IO
131
IO
134
IO
135
IO
137
IO
138
IO
9
IO
12
IO
5
IO
7
IO
11
IO
4
O
SPI0, I2C0, and I2C1 Serial Port Pins
111
IO
110
IO
108
IO
107
IO
105
IO
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u163
y
i
http://www.xiaoyu163.com
2 9
8
PULL
GPIO
DESCRIPTION
McASP0 and McASP1 Receive Master Clock
-
Y
McASP0 Receive Bit Clock
-
Y
McASP0 Receive Frame Sync (L/R Clock)
-
Y
McASP0 and McASP2 Transmit Master Clock
-
Y
McASP0 Transmit Bit Clock
-
Y
McASP0 Transmit Frame Sync (L/R Clock)
-
Y
McASP0 MUTE Output
-
Y
McASP0 Serial Data 0
-
Y
McASP0 Serial Data 1
-
Y
McASP0 Serial Data 2
-
Y
-
Y
McASP0 Serial Data 3
McASP0 Serial Data 4
-
Y
-
Y
McASP0 Serial Data 5 or SPI1 Slave Chip Select
-
Y
McASP0 Serial Data 6 or SPI1 Enable (Ready)
McASP0 Serial Data 7 or SPI1 Serial Clock
-
Y
Q Q
3
6 7
McASP0 Serial Data 8 or McASP1 Serial Data 5 or
1 3
-
Y
SPI1 Data Pin Slave Out Master In
McASP0 Serial Data 9 or McASP1 Serial Data 4 or
-
Y
SPI1 Data Pin Slave In Master Out
McASP0 Serial Data 10 or McASP1 Serial Data 3
-
Y
-
Y
McASP0 Serial Data 11 or McASP1 Serial Data 2
-
Y
McASP0 Serial Data 12 or McASP1 Serial Data 1
-
Y
McASP0 Serial Data 13 or McASP1 Serial Data 0
-
Y
McASP0 Serial Data 14 or McASP2 Serial Data 1
-
Y
McASP0 Serial Data 15 or McASP2 Serial Data 0
-
Y
McASP1 Receive Bit Clock
-
Y
McASP1 Receive Frame Sync (L/RClock)
-
Y
McASP1 Transmit Master Clock
-
Y
McASP1 Transmit Bit Clock
-
Y
McASP1 Transmit Frame Sync (L/RClock)
-
Y
McASP1 MUTE Output
-
Y
SPI0 Data Pin Slave Out Master In or I2C0 Serial Data
-
Y
SPI0 Data Pin Slave In Master Out
-
Y
SPI0 Serial Clock or I2C0 Serial Clock
-
Y
SPI0 Slave Chip Select or I2C1 Serial Clock
-
Y
SPI0 Enable (Ready) or I2C1 Serial Data
co
.
TX-SR504/504E/8450
9 4
2 8
1 5
0 5
8
2 9
9 4
m
9 9
2 8
9 9
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