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Intersil HI5905EVAL2 User Manual

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Description
The HI5905EVAL2 evaluation board allows the circuit
designer to evaluate the performance of the Intersil HI5905
monolithic 14-bit, 5MSPS analog-to-digital converter (ADC).
As shown in the Evaluation Board Functional Block Diagram,
the evaluation board includes sample clock generation
circuitry, a single-ended to differential analog input amplifier
configuration and digital data output latches/buffers. The
buffered digital data outputs are conveniently provided for
easy interfacing to a ribbon connector or logic probes. In
addition, the evaluation board includes some prototyping area
for the addition of user designed custom interfaces or circuits.
The sample clock generator circuit accepts the external
sampling signal through an SMA type RF connector, J2. This
input is AC-coupled and terminated in 50Ω allowing for
connection to most laboratory signal generators. In addition,
the duty cycle of the clock driving the A/D converter is
Evaluation Board Functional Block Diagram
CLK IN
J2
50Ω
ANALOG
IN
J1
50Ω
DGND
AGND
HI5905EVAL2 Evaluation Board User's Manual
Application Note
TTL COMPARATOR
+5V
-5V
D
D
G = +1
G = -1
+5V
-5V
+5V
-5V
D
D
A
A
3-1
1-888-INTERSIL or 321-724-7143
January 1999
adjustable by way of a potentiometer. This allows the effects
of sample clock duty cycle on the HI5905 to be observed.
The analog input signal is also connected through an SMA
type RF connector, J1, and applied to a single-ended to
differential analog input amplifier. This input is AC-coupled
and terminated in 50Ω allowing for connection to most
laboratory signal generators. Also, provisions for a
differential RC lowpass filter is incorporated on the output of
the differential amplifier to limit the broadband noise going
into the HI5905 converter.
The digital data output latches/buffers consist of a pair of
74ALS574A D-type flip-flops. With this digital output
configuration the digital output data transitions seen at the
I/O connector are essentially time aligned with the rising
edge of the sampling clock.
CLK
V
REFOUT
V
REFIN
V
IN+
14
D
-D
0
13
V
IN-
HI5905
|
Intersil and Design is a trademark of Intersil Corporation.
CLOCK
OUT
(CLK)
14
DIGITAL
D
Q
DATA
OUT
>
(D0 - D13)
©
|
Copyright
Intersil Corporation 2000
AN9785

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Summary of Contents for Intersil HI5905EVAL2

  • Page 1 The HI5905EVAL2 evaluation board allows the circuit adjustable by way of a potentiometer. This allows the effects designer to evaluate the performance of the Intersil HI5905 of sample clock duty cycle on the HI5905 to be observed. monolithic 14-bit, 5MSPS analog-to-digital converter (ADC).

  • Page 2: Analog Input

    Application Note 9785 Reference Generator, V and V The difference between the converter's two internally ROUT generated voltage references is 2V. For the AC coupled The HI5905 has an internal reference voltage generator, differential input (Figure 1), if V is a 2V sinewave with -V therefore no external reference voltage is required.
  • Page 3 The HI5905 clock input TABLE 1. HI5905EVAL2 EVALUATION BOARD POWER trigger level is approximately 1.5V. Therefore, the duty cycle SUPPLIES of the sampling clock should be measured at this 1.5V...
  • Page 4 HI5905EVAL2 Figure 4 shows the test system used to perform dynamic EVALUATION BOARD testing on high-speed ADCs at Intersil. The clock (CLK) and analog input (V ) signals are sourced from low phase noise HP8662A synthesized signal generators that are phase locked DAS9200 to each other to ensure coherence.
  • Page 5 Application Note 9785 HI5905EVAL2 Typical Performance (Input Amplitude at -0.5dBFS) INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) FIGURE 5. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT FIGURE 6. TOTAL HARMONIC DISTORTION (THD) vs INPUT FREQUENCY FREQUENCY INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) FIGURE 7.

  • Page 6: Appendix A Board Layout

    Application Note 9785 Appendix A Board Layout FIGURE 11. HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT (NEAR SIDE) FIGURE 12. HI5905EVAL2 EVALUATION BOARD COMPONENT NEAR SIDE (LAYER 1)
  • Page 7 Application Note 9785 Appendix A Board Layout (Continued) FIGURE 13. HI5905EVAL2 EVALUATION BOARD GROUND PLANE LAYER (LAYER 2) FIGURE 14. HI5905EVAL2 EVALUATION BOARD POWER PLANE LAYER (LAYER 3)
  • Page 8 Application Note 9785 Appendix A Board Layout (Continued) FIGURE 15. HI5905EVAL2 EVALUATION BOARD COMPONENT FAR SIDE (LAYER 4) FIGURE 16. HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT (FAR SIDE)
  • Page 9 4.7µF 0.1µF 0.1µF 4.99K 4.7µF 0.1µF D0 - D13, CLK 4.99K 4.7µF 0.1µF 0.1µF ‘ALS574 GND1 HI5905 GND2 ‘ALS574 0.1µF ALS04 0.1µF 0.1µF 4.7µF ALS04...

  • Page 10: Appendix B Schematic Diagrams

    Application Note 9785 Appendix B Schematic Diagrams (Continued) 4.7µF 0.1µF ANALOG 0.1µF 0.1µF 56.2 OPA628AU 0.1µF 4.7µF 22.1 0.1µF 4.7µF 4.7µF 0.1µF 0.1µF OPA628U 0.1µF 4.7µF 4.7µF 0.1µF 0.1µF CLK IN 49.9 MAX9686BCSA 0.1µF 4.7µF 3(CW) 1 (CCW) 0.1µF 0.1µF 3-10...
  • Page 11 Application Note 9785 Appendix B Schematic Diagrams (Continued) D0 - D13, CLK 0.1µF ALS04 ALS04 ALS04 ALS04 3-11...
  • Page 12 +5VAIN +5VDIN (A/D AV , OP-AMPS) (COMPARATOR, D-FF AND INVERTER VIA LPF) AGND DGND 0.1µF 4.7µF 0.1µF 4.7µF AGND AND DGND TIE TOGETHER AT A SINGLE POINT WHERE THE POWER SUPPLIES ENTER THE PWB E11 E12 +5VD1IN -5VAIN (A/D DV (OP-AMPS) AGND DGND...

  • Page 13: Appendix C Parts List

    TP1, 2, 3, 4 Test Point error correction logic. The output of each subconverter Intersil HI5905IN, 14-Bit 5 stage is input to a digital delay line which is controlled by MSPS A/D Converter the internal clock. The function of the digital delay line is to...
  • Page 14 Application Note 9785 correction logic uses the supplementary bits to correct any error that may exist before generating the final fourteen-bit φ φ digital data output (D0-D14) of the converter. φ Because of the pipeline nature of this converter, the digital data representing an analog input sample is presented on φ...
  • Page 15 Application Note 9785 HI5905 Functional Block Diagram BIAS CLOCK ROUT STAGE 1 4-BIT 4-BIT FLASH D13 (MSB) ∑ STAGE 4 4-BIT 4-BIT FLASH ∑ D0 (LSB) STAGE 5 4-BIT GND2 FLASH GND1 3-15...

  • Page 16: Appendix E Pin Descriptions

    Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

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