Casio SF-8350 Service Manual & Parts List page 19

4) Power supply for LCD
(Pin69)
INT1
CPU
V2ON
µ
PD3055GF002-2BA
When the system is start up, CPU will send "H" signal to VIN terminal of gate array from V2ON
terminal. Then, gate array will send "H" signal from VOT terminal to release interruption signal
INT1 of CPU and also, it will be sent to PDB terminal of power supply chip to generate LCD drive
voltages.
5) ROM driving transistor
(Pin35)
" L "
VOB
GATE ARRAY
µ
PD65005G-452-22
After gate array send VOT signal, gate array send "L" signal from VOB terminal to base terminal of
transistor Q1. Then, the VDD is applied to ROM (operation program), CPU can read a ROM
program data by E0 signal.
(Pin30)
"H"
VIN
(Pin45) (Pin29)
GATE ARRAY
µ
PD65005G-452-22
VDD
(Pin1)
R4
(Pin2)
Transistor Q1
(Pin3)
VCC
VDD
µ
PD23C4001
— 18 —
"H"
(Pin31)
VOT
POWER SUPPLY CHIP
SC371015FU
ROM
DATA
EBGW-301
ADDRESS
PDB
LCD drive voltages
VREG,V1~V4
(Pin30)
E0
CPU
µ
PD3055GF002-2BA