Sanyo PLC-XF70 Service Manual page 144

Control Port Functions
PIN NO. NAME
138 PTD[5] / CL1
139 Vcc
140 PTD[7] / DON
141 PTE[6] / M_DISP
142 PTE[3] / FLM
143 PTE[0] / TDO
144 PCC0RESET / DRAK0
145 PCC0DRV / DACK0
146 WAIT
147 RESETM
148 ADTRG / PTH[5]
149 IOIS16 / PTG[7]
150 ASEMD0
151 PTG[5] / ASERKAK
152 PTG[4}
153 PCC0BVD2 / PTG[3] / AUDATA[3]
154 PCC0BVD1 / PTG[2] / AUDATA[2]
155 Vss
156 PCC0BCD2 / PTG[1] / AUDATA[1]
157 Vcc
158 PCC0BCD1 / PTG[0] / AUDATA[0]
159 VssQ
160 PTF[7] / PINT[15] / TRST
161 VccQ
162 PTF[6] / PINT[14] / TRST
163 PTF[5] / PINT[13] / TDI
164 PTF[4] / PINT[12] / TCK
165 PTF[3] / PINT[11]
166 PCCREG / PTF[2] / RESARVATION
167 PCCVS1 / PTF[1] / RESARVATION
168 PCCVS2 / PTF[0] / RESARVATION
169 MD0
170 Vcc_PLL1
171 CAP1
172 Vss_PLL1
173 Vss_PLL2
174 CAP2
175 Vcc_PLL2
176 PCC0WAIT / PTH[6] / AUDCK
177 Vss
178 Vcc
179 XTAL
180 EXTAL
181 LCD15 / PTM[3] / PINT[10]
182 LCD14 / PTM[2] / PINT[9]
183 LCD13 / PTM[1] / PINT[8]
184 LCD12 / PTM[0]
185 STATUS0 / PTJ[6]
186 STATUS1 / PTJ[7]
187 CL2
188 VssQ
189 CKIO
190 VccQ
191 TxD0 / SCPT[0]
192 SCK0 / SCPT[1]
193 TxD_SIO / SCPT[2]
194 SIOMCLK / SCPT[3]
195 TxD2 / SCPT[4]
196 SCK_SIO / SCPT[5]
197 SIOFSYNC / SCPT[6]
198 RxD0 / SCPT[0]
199 RxD_SIO / SCPT[2]
200 Vss
201 RxD2 / SCPT[4]
202 Vcc
203 SCPT[7] / CTS2 / IRQ5
204 LCD11 / PTC[7] / PINT[3]
FUNCTION NAME FUNCTION
PW_RESET PW Reset Signal
1.9V
SH_PW_0 SH Reset Software Protect
NIOS_FPGA_DATA Configuration data Pin
SF_BSY DPRAM Access Control (Output)
TDO [ICE] Test Data Output
not used PCC Reset / DMA Demand receipt
not used PCC Buffer Control / DMA Acknowlege 0
not used Hardware Wait
RESETM Manual Reset Demand
not used Analog Trigger / Input Port H
not used IOIS16(PCMCIA) / Input Port G
ASSEMD0[ICE] ASE Mode
ASEBRKAK [ICE] ASE Break Acknowlege
not used Input Port G
AUDATA[3] AUDATA[3]
AUDATA[2] AUDATA[2]
GND
AUDATA[1] AUDATA[1]
1.9V
AUDATA[1] AUDATA[0]
GND
TRST Test Reset
3.3V
TMS Test Mode Switch
TDI Test Data Input
TCK Test Clock
not used Input Port F / Port Interrupt / Resarvation
not used PCC REG / Input Port F / Resarvation
not used PCC VS1 / Input Port F / Resarvation
MOTHER_FPGA_NSTATUS Error Detect
MD0 Setting Clock Mode
1.9V Power PLL1
CAP1 PLL1 External Capacity Terminal
GND
GND
CAP2 PLL2 External Capacity Terminal
1.9V Power PLL1
AUDCK AUD Clock
GND
1.9V
not used Clock Oscilator
EXTAL External Clock / Crystal Oscilator [33.33333MHz]
MOTHER_FPGA_DONE AUD Clock / Configuration Process End Signal
SH_CHK_DPRAM PW_INT Clear Monitor (Input)
NIOS_FPGA_NSTATUS Error Detect
NIOS_FPGA_DONE Normary Ends Detect
READY_LED Ready LED Output
IC_RESET_CPU IC Power Conyrol
SH_FLASH_WP Flash Write Protect
GND
CKIO System Clock Input / Output
3.3V
SH_LB_UART Send Data (Network)
not used Serial Clock 0 / SCI IO Port
not used SIOF Send Data / SCI Output Port
not used SIOF Clock Input / SCI IO Port
SH_EX_UART Send Data ( External)
not used SIOFClock / SCI IO Port
not used SIOF Flame Sync / SCI Output Port
LB_SH_UART Receive Data (Network)
not used SIOF Receive Data / SCI INput Port
GND
EX_SH_UART Receive Data (external)
1.9V
SH_IRQ_SHUT Shutter Interrupt
SH_SDA_Slot4 IIC Bus (Slot4)
-144-
19200bps / 9600bps
POLARITY I/O
O
" L" : E n a b l e
O
"H" :disable
O
"L" : BYSY O
O
O
O
I
I
I
I
I
O
I
O
O
O
O
I
I
I
I
I / I / O
O / I / O
I / I / O
I
Always : L O / I / O
I
O
I
I
"L" : Non Clear I
I
I
"H" : ON O
O
O
I / O
1 9 2 0 0 b p s /
O
9600bps
IO / IO
O / O
I / IO
1 9 2 0 0 b p s /
O
9600bps
IO / IO
IO / IO
1 9 2 0 0 b p s /
I
9600bps
I / I
I
I / I / I
"L" : Active IO