Sanyo PLC-XF70 Service Manual page 143

Control Port Functions
PIN NO. NAME
69 A6
70 A7
71 A8
72 A9
73 A10
74 A11
75 VssQ
76 A12
77 VccQ
78 A13
79 A14
80 A15
81 A16
82 A17
83 A18
84 A19
85 A20
86 VssQ
87 A21
88 VccQ
89 A22
90 A23
91 Vss
92 A24
93 Vcc
94 A25
95 BS / PTK[4]
96 RD
97 WE0 / DQMLL
98 WE1 / DQMLU / WE
99 WE2 / DQMUL / ICIORD / PTK[6]
100 VssQ
101 WE3 / DQMUU / ICIOWR / PTK[7]
102 VccQ
103 RD / WR
104 PTE[7] / PCC0RDY / AUDSYNC
105 CS0
106 CS2
107 CS3
108 CS4 / PTK[2]
109 CS5 / CE1A / PTK[3]
110 CS6 / CE1B
111 CE2A / PTE[4]
112 CE2B / PTE[5]
113 AFE_HC1 / USB1d_DPLS / PTK[0]
114 AFE_RLYCNT / USB1d_DMNS / PTK[1]
115 VssQ
116 AFE_SCLK / USB1d_TXDPLS
117 VccQ
118 PTM[7]/PINT[7]/AFE_FS/USB1d_RCV
119 PTM[6]/PINT[6]/AFE_RXIN/USB1d_SPEED
120 PTM[5]/PINT[5]/AFE_TXOUT/USB1d_TXSE0 not used
PTM[4]/PINT[4]/AFE_RDET/
121
USB1d_TXDMNS
122 RESARVATION / USB1d_SUSPEND
123 USB1_ovr_crnt / USBF_VBUS
124 USB2_ovr_crnt
125 RTS2 / USB1d_TXENL
126 PTE[2] / USB1_pwr_en
127 PTE[1] / USB2_pwr_en
128 CKE / PTK[5]
129 RAS3 / PTJ[0]
130 PTJ[1]
131 RESARVATION / CAS / PTJ[0]
132 VssQ
133 PTJ[3]
134 VccQ
135 PTJ[4]
136 PTJ[5]
137 Vss
FUNCTION NAME FUNCTION
SH_A6 Adress bus
SH_A7 Adress bus
SH_A8 Adress bus
SH_A9 Adress bus
SH_A10 Adress bus
SH_A11 Adress bus
GND
SH_A12 Adress bus
3.3V
SH_A13 Adress bus
SH_A14 Adress bus
SH_A15 Adress bus
SH_A16 Adress bus
SH_A17 Adress bus
SH_A18 Adress bus
SH_A19 Adress bus
SH_A20 Adress bus
GND
SH_A21 Adress bus
3.3V
SH_A22 Adress bus
SH_A23 Adress bus
GND
SH_A24 Adress bus
1.9V
SH_A25 Adress bus
BS [ICE] Bus Cycle Start Signal
RD
WE0 D7 - D0 Select Signal / DQM (SDRAM)
WE1 D15 - D8 Select Signal / DQM (SDRAM)
WE2 D23 - D16 Select Signal / DQM (SDRAM)
GND
WE3 D31 - D24 Select Signal / DQM (SDRAM)
3.3V
RDWR Read / Write
AUDSYNC ADU SYNC
CS0 Chip Select 0 Flash Memory [16bit]
CS2 Chip Select 2 Divice1 [16bit]
CS3 Chip Select 3 SDRAM [32bit]
CS2 Chip Select 4 Divice2 [16bit]
not used Chip Select 5 Divice3 [8bit]
not used Chip Select 6 Divice4 [8bit]
ON_15V LCD Panel Drive Power Control
not used Setting DPRAM
MOTHR_FPGA_CCLK Clock Pin for Configuration
MOTHR_FPGA_PROG Configuration Start Pin
GND
not used AFE CLOCK
3.3V
not used not used
not used not used
not used
PW_BSY DPRAM Access Control (Input)
not used Resarvation / Transceiver Suspend Output
USBF_VBUS [Func] USB Function Bus
not used USB Host2 Over_Current Detect
not used SCIF RTS Terminal / USB Output Enable Terminal
USB_pwr_en [Func] USB1 Voltage Control
not used USB2 Voltage Control
CKE CK Enable (SDRAM)
RAS3 RAS for SDRAM
SH_EEP_WP EEPROM Write Protect
CAS CAS for SDRAM
GND
MOTHER_FPGA_DATA Configuration Data Pin
3.3V
NIOS_FPGA_CCLK Configuration Clock Pin
NIOS_FPGA_PROG Configuration Start Pin
GND
-143-
POLARITY I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
"L" : BYSY I
O
I
I
O
O
O
O
O
O
O
O
O
O