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IC BLOCK DIAGRAM & DESCRIPTION
IC800 ZR36748 (AV Decorder)
Pin No.
172
173
170
175
Digital video port, CPU and ADP test (8 pin)
199
ICETMS#
GPCI/O[22]
201
GPCI/O[23]
200
ICETDO#
GPCI/O[24]
198
GPCI/O[25]
202
GPCI/O[46]
203
GPCI/O[47]
205
204
Digital audio port (11 pin)
179
181
186,187
AOUT[2:1]
184
192
188
190
182
162
193
PLLCFGA#
GPCI/O[21]
Name
I/O
Y/R/V
AO
YC O : Y signal O.
(DAC B)
RGB O : R signal O.
YUV O : V signal O.
C/B/U
AO
YC O : C signal O.
(DAC C)
RGB O : B signal O.
YUV O : U sibnal O.
CVBS/C
AO
Which CVBS signal or C signal O.
(DAC D)
Select be unrelated to YC / RGB / YUV mide.
RSET
AI
DAC adjusting resistor connect.
VID[7]#
O#
ITU-R656 conform Y / C multiplex digital video O.
I#
ADP ICE interface modo select I.
I/O
Controled general I / O by microcomputer software.
VID[6]#
O#
ITU-R656 conform Y / C multiplex digital video O.
ICETDI#
I#
ADP ICE interface data I.
I/O
Coutroled general I / O by microcomputer software.
VID[5]#
O#
ITU-R656 conform Y / C multiplex digital video O.
O#
ADP ICE interface data O.
I/O
Controled general I / O by microcomputer software.
VID[4]#
O#
ITU-R656 conform Y / C multiplex digital video O.
ICETCK#
I#
ADP ICE interface clock I.
I/O
Controled general I / O by microcomputer software.
VID[3]
O#
ITU-R656 conform Y / C multiplex digital video O.
JTCK#
I#
CPU JTAG clock I.
I/O
Controled general I / O by microcomputer software.
VID[2]#
O#
ITU-R656 conform Y / C multiplex digital video O.
JTMS#
I#
CPUJTAG tms I.
I/O
Controled general I / O by microcomputer software.
VID[1]#
O#
ITU-R656 conform Y / C multiplex digital video O.
JTDI#
I#
CPUJTAG data I.
PUPRD
I
Probe UART data I.
VID[0]#
O#
ITU-R656 conform Y / C multiplex digital video O.
JTDO#
O#
CPUJTAG data O.
PUPTD
O
Probe UART data O.
AMCLK
I/O
Audio master clock I / O.
128,192,256 or 384fs sampling frequency (Programable) use.
S/PDIF
O
S / PDIF O.
N / C
AOUT[0]
O
Digital stereo audio serial data O.
Digital stereo audio serial data I.
AIN
I
ALRCLK
O
Digital stereo audio bit clock O.
Palarity is programable.
ABCLK
O
Digital stereo audio LR clock O.
AOUT and AIN data output or latch, clock trailing edge or
last transition edge(programable).
Controled general I / O by ADP software.
GPAI/O
I/O
GCLK1
ID
27.000MHz clock I for audio master clock generating.
Connected to GCLK when usually operation.
ID#
Audio PLL set I.
Can change when RESET# signal assert.
Uqually operation : low RESET# signai assert term.
Controled general I / O by microcomputer softwaer.
I/O
Function
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