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IC BLOCK DIAGRAM & DESCRIPTION
IC800 ZR36748 (AV Decorder)
Pin No.
Boot selection, debug interface, GPIO pin, test mode (23pin)
40
BOOTSEL1
GPCI/O[0]#
208
2
41
42
GPCI/O[2]#
43
44
45~47
GPCI/O[5-7]
49
GPCI/O[8]#
51
GPCI/O[9]#
8
GPCI/O[10]#
7
GPCI/O[11]#
5,6
GPCI/O[12-13]
4
GPCI/O[14]
197
GPCI/O[15]#
196
GPCI/O[16]#
195
GPCI/O[17]#
177
GPCI/O[18]#
3
GPCI/O[19]#
BOOTSEL2
206
TESTMODE
PLL signal (4 pin)
157
161
160
194
PLLCFGP#
GPCI/O[20]
Analog video port (5pin)
169
Name
I/O
I#
CPU software starting basis select I. Low:starting by flash memory.
High : starting by down loaded program from UART.
I/O#
Controled general I/O by microcomputer software.
NMI
I
MN1 interrupt I.
DUPTD
O
Debug UART data O.
DUPRD
I
Debug UART (or IrDA) data I.
GPCI/O[1]
I/O
Controled general I/O by microcomputer software.
USE general interrupt I.
I/O#
Controled general I/O by microcomputer software.
Use general interrupt I.
SSCSRQ
I
SSC mode : synchronization communication requeat reception.
GPCI/O[3]
I/O
Controled general I/O by microcomputer software.
Use general interrupt I.
GPCI/O[4]
N/C
I/O
Controled general I/O by microcomputer software.
Use general interrupt I.
I/O
Controled general I/O by microcomputer software.
Use general interrupt I.
SSCRXD
I
SSC mode : synchronization communication data reception.
I/O
Controled general I/O by microcomputer software.
SSCTXD
O
SSC mode : synchronization communication data transmission.
I/O#
Controled general I/O by microcomputer software.
SSCCLK
I
SSC made : synchronization communication clock reception.
I/O#
Controled general I/O by microcomputer software.
SSCRRQ
O
SSC mode : synchronization communication acknowledge transmission.
I/O
Controled general I/O by microcomputer software.
I/O
Controled general I/O by microcomputer software.
I/O#
Controled general I/O by microcomputer software.
HSYNC
O
Horizontal synchronization O.
I/O#
Controled general I/O by microcomputer software.
VSYNC
O
Vertical synchronization O.
I/O#
Controled general I/O by microcomputer software.
VCLK x 2
O
VCLK x 2 O.
I/O#
Controled general I/O by microcomputer software.
COSYNC
O
Cosync O.
I/O#
Controled general I/O by microcomputer software.
I
Readed by BOOT ROM after hardware reset and used when select flash
ROM or flash ROM + SRAM set.
ID
Direct connect to GNDP when usually operation.
RESET#
ID
Reset I (Active low).
Initialize process start RESET# signal deassert.
GCLK
ID
27.000MHz clock for main process generation or xtal I.
XO
AO
Connected xyal to GCLK O.
N/C when not use xtal.
ID#
Process clock PLL set I.
Can change when RESET# assert.
Usually operation : low, RESET assert term.
I/O
Controled general I/O by microcomputer software.
CVBS/G/Y
AO
YC O : CVBS signal O.
(DAC A)
RGB O : G signal O.
YUV O : Y signsl O.
Function
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