Figure 8-171.Memory Interface Circuit - Motorola APX 1000 Detailed Service Manual

8-354
DDR INTERFACE
U6302
OMAP1710
D9 DDR_CLKX_1
SDCLKX
C9 DDR_CLK_1
SDCLK
H12 DDR_CLKE
SDCLK_EN
DDR_WE
H8
NSWE
B3 DDR_BANK0
SBANK_0
C3 DDR_BANK1
SBANK_1
0 D6 H7 DDR_RAS
CONTROL
SDATA_0 NSRAS
C6 B4 DDR_CAS
1
SDATA_1 NSCAS
2 C5 G8 DDR_CS
SDATA_2 CS_SDRAM
3 D7 D10 DDR_UDM
SDATA_3 NSDQMU
4 D5 C8 DDR_LDM
SDATA_4 NSDQML
C7 C14 DDR_DQSH
5
SDATA_5 DSQ_H
6 C4 D4 DDR_DQSL
SDATA_6 DSQ_L
7 D8 A2 0
SDATA_7 SADD_0
8 C10 B2 1
SDATA_8 DATA SADD_1
9 D14 B6 2
SDATA_9 SADD_2
10 D11 A1 3
SDATA_10 SADD_3
11 C13 G10 4
SDATA_11 SADD_4
12 C11 B9 5
SDATA_12 SADD_5
13 D13 G12 6
SDATA_13 SADD_6
D12 G11
14 7
SDATA_14 ADDRESS SADD_7
15 C12 G9 8
SDATA_15 SADD_8
B12 9
SADD_9
B8 10
SADD_10
H10
11
SADD_11
H9 12
SADD_12
H11 13
SADD_13
DDR_DATA<17..0>
MMC INTERFACE
F2_TIMER_OUT
U6302
V11
MMC1_CLK
M15
OMAP1710
MMC1_CLKIN
P11
MMC1_CMD
P19
MMC1_CMDDIR
P20
MMC1_DATDIR0
P18
OPTION CARD INTF MMC1_DATDIR1
M14
MMC1_DATDIR2
R18
MMC1_DATDIR3
R11
MMC1_DAT0
V10
MMC1_DAT1
W10
MMC1_DAT2
W11
MMC1_DAT3
Y10
MMC2_CLK
Y8
MMC2_CMD
V9
MMC2_CMDDIR
V5
MMC2_DATDIR0
MEMORY CARD INTF W19
MMC2_DATDIR1
W8
MMC2_DAT0
V8
MMC2_DAT1
W15
MMC2_DAT2
R10
MMC2_DAT3
Figure 8-171. Memory Interface Circuit
V_EXT_1.85
R6301
TP6307
10K
TEST_POINT
DNP
TP6308
TEST_POINT
U6301
DNP
MT46H16M16LF
G2
CLK
G3
CLK*
G1
0
EN_CLKE
1
2 0 DDR_WE G7
WE
3 4 DDR_CAS G8
CAS
DDR_RAS G9
4 3
RAS
5 DDR_CRTL<6..0> 5 DDR_CS H7
EN_CS
1 DDR_BANK0 H8
BA0
H9
2
BA1
0 J8
A0
1 J9
A1
2 DDR_ADDR<2> K7
A2
3 DDR_ADDR<3> K8
A3
DDR_ADDR<4>
4 K2
A4
5 DDR_ADDR<5> K3
A5
6 DDR_ADDR<6> J1
A6
7 DDR_ADDR<7> J2
A7
DDR_ADDR<8> J3
8
A8
9 DDR_ADDR<9> H1
A9
10 DDR_ADDR<10> J7
A10_AP
11 DDR_ADDR<11> H2
A11
DDR_ADDR<12> H3
12
A12
DDR_UDM F2
UDM
DDR_LDM F8
LDM
DDR_ADDR<13..0> 13
R6305
0
RSW_A
OUT
TP6301
1 TEST_POINT
AVR_STATUS_1.8V
DNP
OUT
R6307
0
RSW_B
OUT
R63050
0
RSW_INT
OUT
Schematics, Boards Overlays, and Parts Lists: Transceiver (RF) Boards: 900 MHz (84012478001)
1
TP6304 DNP
TEST_POINT DNP
TP6303
1
TEST_POINT
E2 DDR_DQSH
UDQS
E8 DDR_DQSL
LDQS
A8 0
DQ0 DDR_DATA<0>
B7 1
DQ1 DDR_DATA<1>
B8 2
DQ2 DDR_DATA<2>
C7
3
DDR_DATA<3>
DQ3
C8 4
DQ4 DDR_DATA<4>
D7 5
DQ5 DDR_DATA<5>
D8 6
DQ6 DDR_DATA<6>
E7
7
DDR_DATA<7>
DQ7
E3 8
DQ8 DDR_DATA<8>
D2 9
DQ9 DDR_DATA<9>
D3 10
DQ10 DDR_DATA<10>
C2 11
DDR_DATA<11>
DQ11
C3 12
DDR_DATA<12>
DQ12
B2 13
DQ13 DDR_DATA<13>
B3 14 PA_SHTDN
DQ14 DDR_DATA<14>
A2 15
DQ15 DDR_DATA<15>
F3
PA_SHTDN
NC1 NC
F7
NC2
R6492 FLASH INTERFACE
1.8K
0 1 TP6305 DNP
TEST_POINT
U6302
8 1
TP6306 DNP
OMAP1710
TEST_POINT
L4
NF_ADV
M7
NFCS_0
M3
NFCS_1
M4
NFCS_2
N8
NFCS_3
U4
NFOE
CONTROL
W1
NFRP
W2
NFWE
V4
NFWP
0 N4 N3
FDATA_0 FCLK
1 N2 V2
FDATA_1 FRDY
2 N7 J8
FDATA_2 FADD_1
3 P2 D3
FDATA_3 FADD_2
P4 C1
4
FDATA_4 FADD_3
5 P7 E4
FDATA_5 FADD_4
6 R2 D2
FDATA_6 FADD_5
7 R3 F4
FADD_6
FDATA_7
R4 E3
8
FDATA_8 DATA FADD_7
9 T2 J7
FDATA_9 FADD_8
10 T3 F3
FDATA_10 FADD_9
11 P8 G4
FDATA_11 FADD_10
U1 G3
12
FDATA_12 FADD_11
13 U3 G2
FDATA_13 FADD_12
14 T4 K8
FDATA_14 ADDRESS FADD_13
15 V3 H4
FDATA_15 FADD_14
H3
FADD_15
K7
FADD_16
J2
FADD_17
J4
FADD_18
J3
FADD_19
F2
FADD_20
L8
FADD_21
K4
FADD_22
K3
FADD_23
L7
FADD_24
E1
FADD_25
V_EXT_1.85
V_EXT_1.85
R6316
10K
FLASH_CTRL<8..0>
R6304
FLASH_RDY 0
7
V_EXT_1.85
R6306
10K
R6314
6 R6310 33
33
0
1 33 E6
R6311
CLK
B4
CE
FLASH_OE_A
2 F8
OE
8 4 R6313 33 G8
WE
TP6302 1 3 D4
RST
TEST_POINT
DNP C6
1 WP
R6312 33 2 0 F6
ADV
3
4
1 A1
A1
6 2 B1
A2
7 3 C1
A3
1 4 D1
A4
2 5 D2
A5
A2
3 6 A6
4 7 C2
A7
5 8 A3
A8
6 9 B3
A9
C3
7 10 A10
8 11 D3
A11
9 12 C4
A12
10 13 A5
A13
B5
11 14 A14
12 15 C5
A15
13 16 D7
A16
14 17 D8
A17
15 18 A7
A18
B7
16 19
A19
17 20 C7
A20
18 21 C8
A21
19 22 A8
A22
G1
20 23 A23
21 24 H8
A24
22 25 B6
A25_512M
23 B8
A26_1G
NC
24
25
FLASH_ADDR<25..1>
FLASH_DATA<15..0>
V_FLASH
C6308 C6309 C6310 C6311
0.1UF 0.1UF 0.1UF 0.1UF
U6304
F7
WAIT
F2 0
DQ0
E2 1
DQ1
G3
DQ2 2
E4 3
DQ3
E5 4
DQ4
G5 5
DQ5
G6
DQ6 6
H7 7
DQ7
E1 8
DQ8
E3 9
DQ9
F3
DQ10 10
F4 11
DQ11
F5 12
DQ12
H5 13
DQ13
G7
DQ14 14
E7 15
DQ15
E8
RFU1
NC
F1
RFU2
NC
G2
RFU3
NC
H1
RFU4
NC