System Clock - Samsung SF11OT Servise Manual

Circuit Description
with TSTCLK high, and an internal wait state
occurs in the TSTCLK (6 MHz). These signals are
sent to the /RD and /WR ports of RAM , ROM,
and the MODEM in order to read or write data
when a chip select line is active.
DO - D7: 8 bit data bus
COMMUNICATION
PRINTER
DATA
CONTROL
AND
SENSORS
The 6 MHz internal clock frequency is generated
by dividing the 12 MHz system clock from
MODEM by two inside the MODEM.
Figure 5-2: XFC Hardware interface Signals
CRYSTAL
BUS
MODEM
Electronics