Integra DTR-5.8 Service Manual page 83

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -48
Q2001: F2628E-01 (XM Digital Transceiver)
TERMINAL DESCRIPTION(2/2)
Pin No. Pin Name
32 HSDP_DATA
34 HSDP_CLK
35 DT4_MODE
36 HSDP_EN#
37 I2S_DATA
39 I2S_SCLK
41 I2S_LRCLK
43 I2S_OCLK
TE
L 13942296513
44 MUTE
45 SAII_CLK
47 SAII_DATA
48 SAII_REQ
Pin#
4, 8, 17, 20,
27, 33, 40, 46
2, 10, 16, 21,
24, 25, 31, 38,
42
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Direction Function in Slave Mode
S=In High Speed Data Port Data
M=Out Input
S=In High Speed Data Port Clock
M=Out Input
Enables/Disables driver on
SC_RATE and ANT_REV
S=In
(High = enable driver) This
M=In
pin was VSS on rev 3
XM/DT IC
S=In High Speed Data Port Enable
M=Out Input (Active low)
S=In
I2S Digital Audio Port Data In
M=Out
S=In I2S Digital Audio Port Bit
M=Out Clock In
S=In I2S Digital Audio Port
M=Out Left/Right Clock In
I2S Digital Audio Port
S=In
Oversample Clock
M=Out
(not used, leave unconnected)
S=n/u Not used in Slave mode, leave
M=Out unconnected
S=Out
SAII Port Clock Output
M=In
S=Out
SAII Port Data Output
M=In
S=In
SAII Port Request Input
M=Out
Pin Name Type
VDD PWR +3.3V Supply Voltage
VSS GND Digital Ground
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2 9
8
Function in Master Mode
High Speed Data Port Data
Output
High Speed Data Port Clock
Output
Enables/Disables drivers on
MUTE and ANT_REV (High
= enable drivers) This pin
was VSS on rev 3 XM/DT IC
High Speed Data Port Enable
Output (Active low)
I2S Digital Audio Port Data
Out
I2S Digital Audio Port Bit
Clock Out
I2S Digital Audio Port
Left/Right Clock Out
I2S Digital Audio Port
Oversample Clock Out
Provides a mechanism for
Q Q
3 6 7 1 3 1 5
muting the audio during an
I2S rate change (High=mute)
SAII Port Clock Input
SAII Port Data Input
SAII Port Request Output
Function
in Slave Mode in Master Mode
+3.3V Supply Voltage
Digital Ground
co
.
9 4 2 8
Notes
Out= 4mA, SLC
In=LVTTL S/T
Out= 4mA, SLC
In=LVTTL S/T
In=LVTTL S/T
Out= 4mA, SLC
In=LVTTL S/T
Out= 4mA, SLC
In=LVTTL S/T
Out= 4mA, SLC
In=LVTTL S/T
Out= 4mA, SLC
In=LVTTL S/T
Out= 4mA, SLC
0 5 8 2 9 9 4 2 8
Out= 4mA, SLC
Out= 4mA, SLC
In=LVTTL S/T
Out= 4mA, SLC
In=LVTTL S/T
Out= 4mA, SLC
In=LVTTL S/T
Function
Notes
m
DTR-5.8
9 9
9 9