Integra DTR-5.8 Service Manual page 65

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -30
Q8001: FLI8125-LF-BC (Video Processor)
TERMINAL DESCRIPTION(3/8)
Low Bandwidth ADC Input Port
Pin Name
LBADC_IN6
LBADC_RTN
VSSA33_LBADC
RCLK PLL Pins
Pin Name
GND_RPLL
VDD_RPLL_18
VBUFC_RPLL
AGND_RPLL
XTAL
TCLK
AVDD_RPLL_33
Digital Video Input Port
TE
L 13942296513
Pin Name
VID_CLK_1
VIDIN_HS
VIDIN_VS
VID_DATA_IN_0
VID_DATA_IN_1
VID_DATA_IN_2
VID_DATA_IN_3
VID_DATA_IN_4
VID_DATA_IN_5
VID_DATA_IN_6
VID_DATA_IN_7
VID_DATA_IN_8
VID_DATA_IN_9
VID_DATA_IN_10
VID_DATA_IN_11
VID_DATA_IN_12
VID_DATA_IN_13
VID_DATA_IN_14
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VID_DATA_IN_15
VID_DATA_IN_16
VID_DATA_IN_17
VID_DATA_IN_18
.
VID_DATA_IN_19
VID_DATA_IN_20
VID_DATA_IN_21
VID_DATA_IN_22
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No I/O Description
a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak).
7 AI Low Bandwidth Analog Input-6. The Input signal connected to this Pin, must be bypassed with
a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak).
8 AG This Pin provides the Return Path for LBADC inputs. Must be directly connected to the analog
system ground plane on board.
9 AG Analog Ground for Low Bandwidth ADC Block. Must be directly connected to the analog
system ground plane on board.
No I/O Description
11 DG Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground
plane.
12 DP Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to Ground Plane.
13 O Test Output. Leave this Pin Open. This is reserved for Factory Testing Purpose.
14 AG Analog ground for the Reference DDS PLL. Must be directly connected to the analog system
ground plane.
15 AO Crystal oscillator output. Connect to external crystal.
16 AI Reference clock (TCLK) from the 19.6608 MHz crystal oscillator. Connect to external crystal/
oscillator.
17 AP Analog Power (3.3V) for RCLK PLL. Must be bypassed with 0.1uF capacitor.
No I/O Description
153 I Video port data clock input meant for Video Input – 1. Up to 135Mhz
[Input, 5V-tolerant]
122 I When Video Input – 1 is in BT656 Mode, this Pin acts as Horizontal Sync Input for Video
Input – 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Horizontal Sync Input for Video
Input – 1.
OR this Pin acts as Horizontal Sync Input for 24 Bit Video Input
121 I When Video Input – 1 is in BT656 Mode, this Pin acts as Vertical Sync Input for Video Input
– 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Vertical Sync Input for Video
Input – 1.
OR this Pin acts as Vertical Sync Input for 24 Bit Video Input
135 IO Input YUV data in 8-bit BT656 of Video Input – 1
136 [Bi-Directional, 5V-tolerant]
137
138 OR Input Y Data in case of 16 Bit Video Input (CCIR601) of Video Input – 1
139
140 OR Input Green Data in case of 24 Bit Video Input
141
142
145 IO Input Pr / Pb Data in case of 16 Bit Video Input (CCIR601) of Video Input – 1
146
147 OR Input Blue/ Pb Data in case of 24 Bit Video Input
148
149
150
151
152
123 IO Input Red / Pr Data in case of 24 Bit Video Input
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124
125 OR Video Input – 2 in 8-bit with Embedded Sync / Separate Sync
i
128
129
130
131
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DTR-5.8
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