Yamaha HTR-6290 Service Manual page 87

A B
1
128Mbit SDRAM
DQ**
EDS1216AATA-75
IC611
2
(+3.3D)
A**
SDCLK=66MHz SDCLK=66MHz
3
+3.3D
1,2
REGULATOR
3
PQ018EZ01ZPH
IC604
4 (3.3V→1.8V)
14.7456MHz
XL602
32.768KHz
XL601
5
6
7
C D
NET SECTION BLOCK DIAGRAM
D[0]~D[15] D[0]~D[15]
A[0]~A[11],A[14],A[15] A[1]~A[21]
DA** AD**
2
CSn[6]
10 194
SDCLK
WRn
208 193
SDCLKEN
RDn
23
DQMn[1]
109
24
DQMn[0]
RXD[0]
14 113
SDWEn
TXD[0]
22
CASn
21 110
RASn
RXD[1]
15
114
SDCSn[3]
TXD[1]
+3.3DC
(RVDD)
125
PRSTn
+1.8DC Reset for EP9301
(CVDD)
MICROPROCESSOR
147
(NET)
EGPIO[4]
EP9301-CQZ
118
148
[166MHz]
XTALI EGPIO[3]
119
XTALO
IC610
157
(RVDD:+3.3DC) USBm[2]
137 158
RTCXTALI (CVDD:+1.8DC) USBp[2]
93
SCLK
94
LRCK
96
SDO0
146
EGPIO[5]
E F
(R, T, K, A, B, G, E, L, J models)
• See page 142, 143 →
NET
32Mbit FLASH-ROM
DQ**
S29JL032H70TFI020
IC613
(+3.3D)
A**
12
/RESET
Reset for FLASH
Serial communication
Between EP9301 and iPod (UART0)
Serial communication
Between EP9301 and main microprocessor (UART1)
Reset from main microprocessor to P.C.B. NET
RESET CIRCUIT
Power on reset
BD4830FVE-TR
IC601
1
USB power enable
2
Error detect
<USB2.0 HOST(Full Speed)>
22.5792MHz
XL751
+5A
LOGIC for AUDIO CLOCK
22.5792MHz
SN74LV163APWR IC615,616
SN74LV74APWR IC617
(+3.3D)
5 11
BICK 7
DAC
AUDIO
LRCK 8
PCM1781DBQR
SDO(I2S) 6
IC751
MUTE 4
(+5A)
G H
• See page 123-125 →
DSP
SCHEMATIC DIAGRAM
SCHEMATIC DIAGRAM
<Power>
1
+3.3D(700mA) 1:+3.3_N
2
DGND 2:NETG
3
+5D (520mA) 3:+5_N
• See page 126-129 →
FUNCTION
SCHEMATIC DIAGRAM
6
1:RXDi(3.3V)
5
2:TXDi(3.3V)
10 11 3
4:TXDNW(5V)
3.3V 5V
9 8 2
5:RXDNW(5V)
74LCX07MTCX
IC614
6 5 1
(+3.3D)
6:NW_RST
4
3:MG
+5D
DGND
+5U for USB(500mA)
7 OPERATION (R, T, K, A, B, G, E, L, J models)
• See page 130 →
POWER DISTRIBUTION
SCHEMATIC DIAGRAM
SWITCH for USB 8
MIC2026-2YM
IC609
1
1:VBus
2
2:-DATA
3
3:+DATA
4
4:GND
5
5:FG
DGND
+12A
• See page 123-125 →
DSP
SCHEMATIC DIAGRAM
DACGND
+12A(50mA)
4
4:+12
15(Lch) 1
1:NETL
IC752 NJM4565M
14(Rch) 3
3:NETR
2
2:E
DACGND DACGND
I J
RX-V1900/HTR-6290/DSP-AX1900
USB
87