Ecleree PAM2600 Service Manual page 18

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BINARY COUNTER HEF4520
This is a 4-bit double binary counter. Configured in a way in which when there is the binary code
equivalent to decimal number 5 at its output -so this is 1 0 0- it is blocked in this position, until it receives a new
MR reset pulse. The blocking action is performed by the NAND gate between legs Q2 and CP1. At this state Q2
becomes "H" one logical, the NAND changes its state putting the leg CP1 to "L" zero logical and -as you can see
in the table of functions- the mode can not change in this conditions.
The general turn-on reset initializes the counter. Every time it receives a pulse from the module
opto-couplers because of a protections shot it is counted. If during an interval of approximately 5 minutes it does
not receive any other pulse, the counter will go back to the original zero state, because it receives a new MR reset
pulse from the monostable IC311, whose time constant is approximately 5 minutes (R342,C319). This
monostable begins counting from the very first pulse received by the counter, because both are linked to the
PROTECT SIGNAL from the module and, consequently, activated at the same time.
If during this time interval (about 5 minutes) a minimum of 5 successive pulses are received, these will
make the counter block at that position. This translates into a logical "1" at the Q2 leg of the counter, a "0" at the
NAND (IC308) output; this zero makes a "1" at the output of the next NAND, giving a result of "0" at the collector
of Q301, so Q302 is not conducting and the relay K301 remains open. It will stay this way until the reset from the
monostable happens or there is a manual mains disconnection by pushing the power off button.
The reset circuit associated with the monostable is made of C320, D320, R339 and D318 (above we
have always been refering to channel L). By means of diodes D317 and D318 we build an "O" gate, with which we
apply any of the above mentioned reset pulses to the counter.
CPO
CP1
8
H
L
9
X
9
X
8
8
L
H
9
X
X
MR
MODE
L
counter advance
L
counter advance
L
no change
L
no change
L
no change
L
no change
H
Q0 to Q3=low
15

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