Atari ST series Technical Reference Manual page 312

register, and an 8-bit interval counter, whose value decre­
ments by one at every impulse. When the interval counter
timer reaches 0, the value of the data register is loaded into
the counter, and an interrupt will be generated if enabled.
The source of the impulse that causes the counter to dec­
rement may be a clock pulse (Delay mode), or an external
signal (Event Count mode). There is also a combined mode
(Pulse Length mode), in which the clock is turned on and off
by the external signal.
The control registers use bits 0-3 to determine the mode
in which the timers will function. The possible combinations
are detailed in Table F-3.
Table F-3. Timer A and B Register Values and Timer Modes
Register Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit four (value of 16) can be used to force a timer reset.
Register 15.
Since Timers C and D only run in Delay mode, only one byte
is needed for their control register. The upper nibble controls
Timers C, while the lower nibble controls timer D, as shown
in Table F-4.
Table F-4. Control Register Values for Timers C and D
Timer C Timer D
Value Value
0 0
16 1
32 2
304
APPENDIX F
Timer Mode
Timer off
Delay mode, clock divided by 4
Delay mode, clock divided by 10
Delay mode, clock divided by 16
Delay mode, clock divided by 50
Delay mode, clock divided by 64
Delay mode, clock divided by 100
Delay mode, dock divided by 200
Event Count Mode
Pulse Length mode, clock divided by 4
Pulse Length mode, clock divided by 10
Pulse Length mode, clock divided by 16
Pulse Length mode, clock divided by 50
Pulse Length mode, clock divided by 64
Pulse Length mode, clock divided by 100
Pulse Length mode, clock divided by 200
Timers C and D Control Register (TCDCR).
Timer off
Delay mode, clock divided by 4
Delay mode, clock divided by 10
Timer Mode