Pin Assignment - Denon DN-D4500 Service Manual

PCM1748 (IC503,553)
1 16
BCK
DATA 2 15
LRCK 3 14
4 13
DGND
PCM1748
V 5 12
DD
V 6 11
CC
V L 7 10
OUT
V R 8 9
OUT
64M SDRAM (IC110,210)
128M SDRAM (IC402)
1 5
TOP VIEW
27
BU2090F (IC702,802)
Vss 1
Control Circuit
DATA 2
12-Bit Shift Register
CLOCK 3
Latch
Q0 4
Output Buffer
(Open Drain)
Q1 5
Q2 6
Q3 7
Q4 8
BCK
SCK
ML
LRCK
MC
MD
ZEROL/NA DATA
ZEROR/ZEROA
V
COM ML
AGND
Function
MC
MD
System Clock
SCK

Pin Assignment

Pin No. Pin Name
22, 23~26, A0~A11 Address
4
29~35
20, 21 BS0, Bank Select
BS1
2, 4, 5, 7, 8, DQ0~ Data Input/Output
10,11, 13, 42, DQ15
44,45, 47, 48,
50, 51, 53
19 CS# Chip Select
18 RAS# Row Address Strobe
17 CAS# Column Address Strobe Referred to RAS#
16 WE# Write Enable
15, 39 UDQM/ input/output mask
LDQM
38 CLK Clock Inputs
28
37 CKE Clock Enable
1, 14, 27 Vcc Power (+3.3V)
28, 41, 54 Vss Ground
3, 9, 43, 49 VccQ Power (+3.3V) for I/O buffer Separated power from Vcc, used for output buffers to improve noise.
6, 12, 46, 52 VssQ Ground for I/O buffer
36, 40 NC No Connection
16 V
DD
15 Q11
14 Q10
13 Q9
12 Q8
11 Q7
10 Q6
9 Q5
Serial
Input
I/F
8x
Oversampling
Digital Filter
Delta-Sigma
with
Function
Controller
Control
I/F
System Clock
Zero Detect
Manager
Function
Multiplexed pins for row and column address.
Row address: A0~A11. Column address: A0~A8.
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
Command input. When sampled at the rising edge of the clock,
RAS#, CAS# and WE# define the operation to be executed.
Referred to RAS#
The output buffer is placed at Hi-A (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated ground from Vss, used for output buffers to improve noise.
No Connection
TPC6103 (IC410)
6
1
22
DN-D4500 / BU4500
Output Amp and
DAC
Low-Pass Filter
Enhanced
Multi-Level
Modulator
Output Amp and
DAC
Low-Pass Filter
Power Supply
Description
5 4
2 3
V L
OUT
V
COM
V R
OUT