Schematic Diagram (Digital) - Yamaha rx-sl100 Service Manual

A B C

SCHEMATIC DIAGRAM (DIGITAL)

1
Q Q
7
3
2
x: NOT USED
O: USED / APPLICABLE
Page 61 J3 Page 60 H1 Page 62
to INPUT (2) to INPUT (1) to MAIN (4)
4M DRAM
3
4.9 0
DIGITAL INPUT
1.6 1.6
1.6 1.6
1.6 1.6
1.7 1.6
4.9 0
2.1 1.6
2.3 1.6
~ 1.6
~ 1.6
2.1
3.0 2.1 0
1.7 3.0 2.5
~ 0.4
1.0 ~ 0
1.7 ~
1.6 1.9 3.7
1.7 1.6
4.9 0
4 Point 3 Pin 1 of IC304
0
0
0
3.3
4.0
0.2
3 1
0.1 0.1
0.3
2 0.8
4.9
4.9
4
5 6 0 0
0
5
STATIC RAM
0
4.9
2.5
0
3
2.5
T E
L 1 3 9 4
6
0 2.9
3.3
2.8
0
2.5
0
2.3 0
CPLD
0 1.3
0.9 0
0.3
0.5
2.5 2.8
7
3.3 3.3
2.6 2.8
0.8 2.8
0.4
4.7
4.9
2.8
4.8
2.8
4.9
0
4.8
0
0
2.6
3.3
2.8
4.9
2.5
0 3.3
8
IC318: W986432DH-7
SDRAM
IC333~336: 74LCX07MTCX IC329: TC74VHCT08AFT
Hex Buffer Quad 2-Input And Gate
VCC 1
DQ0 2
A0 1 14 VCC 1A 1 14 Vcc
VccQ 3
1B 2 13 4B DQ1 4
O0 2 13 A3
DQ2 5
1Y 3 12 4A
GND 6
A1 3 12 O3
2A 4 11 4Y DQ3 7
DQ4 8
2B 5 10 3B
O1 4 11 A4
VccQ 9
9
2Y 6 9 3A
DQ5 10
A2 5 10 O4
GND 7 8 3Y DQ6 11
GND 12
O2 6 9 A5
DQ7 13
NC 14
GND 7 8 O5
VCC 15
DQM0 16
IC330~332, 339: NJM2068MD-TE2
Dual OP-Amp. WE 17
CAS 18
RAS 19
CS 20
OUT 1 1 8 +V CC
NC 21
w w w
A22 22
–IN 1 2 7 OUT 2
A13 23
+ – + –
A12 24
+IN 1 3 6 –IN 2
A2 25
A3 26
–V CC 4 5 +IN 2
A4 27
.
DQM2 28
Vcc 29
NC 30
10
DQ10 31
GND 32
DQ17 33
DQ18 34
VccQ 35
DQ19 36
DQ20 37
GND 38
DQ21 39
DQ22 40
VccQ 41
DQ23 42
Vcc 43
D E F
Page 63 D8 Page 64 D5 Page 64 G8
to POWER (1) to POWER (5) to POWER (4)
1 5 1
6 3
1.6
3.6
2.7
1.4
L7
3.3
0
4.9
0 Point 2 Pin 20 of IC307
0
0
3.7
2.5
3.3
1.8
0
0
0
0
0
0
3.1
0
4.3
5.0
5.0
0.1
2.5 0
2.5
1.6
0
0
1.6
1.6 0
1.6 0
DSP
2.5 0
0 5.0
5.0
4.7 0
4.8
0
0
0
3.3
3.3
1.2 0 0 0 0
0 0 0
1.3 2.9
0
1.3 1.8
0 2.9
3.5
2.8
0 1.1 3.3
4.9 1.6
0
4.9 0
3.2
3.2 5.0
1.6 3.2 5.0 3.2
1.7
1.7
0
0
0
4.0
2.5
0
3.3
3.3
2 2 9 6 5 1 3
0
0 2.5
0 D/A 2.5
1.7
1.7 0
CONVERTER
1.2 2.4
0 2.5
1.3 2.5
1.3
0 2.4
0 2.4
SURROUND L
3.3
3.3 0
DTS-ES /
1.7 1.7
1.7 1.7
1.7 NEO:6 0
FRONT L
2.5 2.5
0 0.9
DECODER
0 2.5
0.9
0.3
2.3 2.5
3.3 3.2
2.5
4.8
2.5
4.9
0.3
0.3
0.3
0
4.8 2.6
3.3
4.9 3.3
4.9 3.3
0
4.8 3.3
3.3 3.3
3.3 3.3
CLK
CLOCK
BUFFER
86 GND
85 DQ15 CKE
84 GND
83 DQ14
82 DQ13
CS CONTROL
81 VccQ SIGNAL
MONITOR
80 DQ12 RAS
COMMAND
79 DQ11
DECODER
CAS
78 GND
COLUMN DECODER COLUMN DECODER
77 DQ10 WE
76 DQ9
75 VccQ
74 DQ8 CELL ARRAY CELL ARRAY
A10/AP
73 NC BANK #0 BANK #0
72 GND
71 DQM1 MODE
REGISTER
70 NC A2
SENSE AMPLIFIER SENSE AMPLIFIER
ADDRESS
69 NC
BUFFER
68 CLK A22
67 CKE
66 A11
65 A10
64 A9
63 A8 x a DATA CONTROL o DQ
CIRCUIT BUFFER y
62 A7
61 A6
REFRESH COLUMN
60 A5
COUNTER COUNTER i
59 DQM3
58 GND
57 NC
56 DQ31
55 VccQ
54 DQ30 COLUMN DECODER COLUMN DECODER
53 DQ29
52 GND
51 DQ28
CELL ARRAY CELL ARRAY
50 DQ27
BANK #0 BANK #0
49 VccQ
48 DQ26
47 DQ25
SENSE AMPLIFIER SENSE AMPLIFIER
46 GND
45 DQ24
44 GND
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Page 60 E1
to INPUT (1)
5
0
4.9
3.0
RGB ENCODER
0.7
0
4.9 1.7
1.3
1.2
1.0
1.3
0
0
5.0
5.0
MICRO COMPUTER 4.9
0
4.9
0
4.9
0
4.9
4.9
1.1
0
4.9
4.9 3.3
4.9 0
3.3
4.8
0
0
4.8 0
0
0
4.9 0
0
4.9 0
4.9 0
4.9 0
0 0
0 0
4.9
0
4.9
3.3
4.9 3.3
0 0
4.9 5.1
2.5 0
0
2 4.9 2.4
4.9
0
0 5.1
3.3
0.8
3.3
0
0 0 0 0 0 0 0 0 0
0 3.6 0 0 4.0 0 1.8 0
0 2.7 3.6 5.4 0 0 4.9
3.3
0 1.4 2.7 0 1.7 4.9 0 0
0 3.3 1.4 5.0 4.9 1.7 0 0 4.9
0
0 3.7 3.3 5.0 5.0 1.6 0 0 0
0 0
0 2.5 3.7 5.0 5.0 1.4 4.9
0 0
0 0.4 2.5 0 0 1.4 0
0 0
0 1.8 3.3 2.9 0 1.9 0
0 3.3
0 0 4.6
1.6 0 1.8 0 0
3.3
1.1 3.2 1.1 3.2 5.0 3.2 5.0 3.2 5.0
1
0
3.2 5.0
5.0 3.2 5.0 3.2 5.0 3.2 5.0
1.6
1.6
3.3
0
3.2
3.2
0
4.9
Q Q
0
3 7 6
3.2
4.9 3.2
0
0
3.2
0
SURROUND BACK
11.8
CENTER
0
0
0
0
0
0 -11.9
3.3 3.3
3.3
11.8 4.9
0
1.1
0 0 0
1.8
0.4 0
2.5 0
3.7 0
3.3 0
1.4 0
0 2.7 0
0
3.6 0
0
-11.9 1.6 0
3.3 1.8
11.8
0
2.8 1.9
3.5 1.4
0 0
2.9 1.6
1.8 1.7
2.9 1.7
3.5 3.4
4.0
0 2.9
0 0 0
0
5.0
0
-11.9
3.3 5.0
11.8
0 5.0
0 0
0
0
0
-11.9
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
IC316: MBM29LV320BE90T IC315: MB3516APF-G-BND
4Mbit Flash Memory RGB Encoder
RY/BY DQ15 to DQ0
GND2 R-OUT G-OUT
RY/BY 24 23 22
Buffer
VCC
VSS Erase Voltage Input/Output
R-output G-output
Generator Buffers
buffer buffer
75 Ω drive 75 Ω drive
WE
State
BYTE Control
RESET
Command
Register
WP/ACC
Program Voltage
DQ0 Generator
u 1 Chip Enable 6 STB Data Latch 3
| Output Enable
DQ31 Logic
CE
OE
.
DQM0~3
Y-Decoder Y-Gating
STB
Timer for
Low Vcc Detector Address
Program/Erase CSYNC
Latch
X-Decoder Cell Matrix
A20 to A0
Clamp Clamp
A-1
1 2 3
GND1 R-IN G-IN
http://www.xiaoyu163.com
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Page 65 F3
to POWER (12)
2 4
8 9 9
3.3
0
1.7
3.3
0
0
3.3
3.3
VIDEO DISPLAY 0
0
0
0
0
0
0
0
0
0
0
0
3.3
0
0
0
0
Point 1 Pin 239 of IC317 0
0
0
0
3.3
3.3
3.3
3.3
0
0
1.8
0.4
2.5
3.7
3.3
1.4
2.7
3.6
0
1.6
3.3
2.8
3.3
3.5
2.9
1.8
2.9
3.5
0
3 1 5 1 5 0 8 9 2
3.2
SDRAM
0
s
IC310~314, 340: 74LVX4245MTCX
8-Bit Dual Supply Translating Transceiver
B-OUT VIDEO-OUT Vcc2 N.C. Y-TRAP Y-OUT CROMA-OUT N.C. N.C.
21 20 19 18 17 16 15 14 13 V CCA
(T R) DIR
A 0
B-output VIDEO Y-output CROMA
A 1
buffer output buffer buffer output buffer
75 Ω drive 75 Ω drive 75 Ω drive 75 Ω drive
A 2
A 3
m
Y/C A
4
MIX
A 5
A
buffer 6
c o
A 7
Y
GND
M
a
GND
R-Y
t LPF R-Y
r
modulation
i
A 0 A 1
x B-Y
LPF B-Y
modulation
CSYNC CSYNC
Burst generation
Phase
Clamp LPF & NTSC/PAL
generation
selection OE
4 5 6 7 8 9 10 11 12 T/R
B-IN N.C. fsc-IN NTSC/PAL-IN N.C. N.C. CSYNC-IN N.C. Vcc1
B 0 B 1
L M N
RX-SL100/RX-SL100RDS
IC301: CY62256LL-70SNCT
Static RAM
2
8 9 9
I/O
A 0
10 INPUT
A 9 BUFFER I/O
1
A
8
A I/O
7 2
A 6
I/O
A 512x512 3
5
A 4 ARRAY I/O
4
A
3
A I/O 5
2
I/O
POWER 6
CE
DOWN I/O
WE COLUMN 7
DECODER
OE
IC302: MSM514260E-60JS
4Mbit DRAM
WE OE
13 27
Timing
RAS 14
Generator
I/O
Controller
LCAS 29
Output
UCAS 8
28 I/O 8
Buffers
Controller
DQ1~DQ8
Column
Input
9 Address 9 Column Decoders
8 8
Buffers
Buffers
Internal I/O
Sense Amplifiers 16 16
Refresh Selector
A0~A8 Address
Control Clock
Counter
Input
8 8
Buffers
Row
Row
9 Address 9 Word Memory
Deco- DQ9~DQ16
Buffers
Drivers Cells
ders
Output
8
8
Buffers
VCC 20
On Chip
VBB Generator
VSS 21
IC303: XC9572XL-10TQ100C
CPLD
3
JTAG
JTAG Port 1 In-System Programming Controller
Controller
54 Function
I/O
Block 1
18
I/O Macrocells
1 to 18
I/O
I/O 54
Function
Block 1
18
Macrocells
1 to 18
I/O
I/O
Blocks
I/O 54 Function
Block 1
18
I/O
Macrocells
1 to 18
I/O
3
I/O/GCK
54
Function
1
I/O/GSR Block 1
18
Macrocells
2
I/O/GTS 1 to 18
4 9 8 2 9 9
IC305 (U, C, R, T, K, B, G model): CS493264-CL
IC305 (J model): CS493292-CLR
Audio Decoder
36 8 9 10 11 14 15 16 17 18 5 4 19 7 6 20 21
DD
37
CMPDAT, SDATAN2, RCV958 27 Parallel or Serial Host Interface
38 DC
Compressed
CMPCLK, SCLKN2 Data Input
28
Frame
Interface
CMPREQ, LRCLKN2 Shifter 24-Bit
29 MCLK
44
DSP Processing
43 SCLK
Input
RAM RAM
Buffer 42 LRCLK
Program Data RAM Output
SCLKN1, STCCLK2 25 Digital
Controller Memory Memory Buffer Output 39 AUDATA2
Audio Formatter AUDATA1
LRCLKN1 26 ROM ROM 40
Input
41 AUDATA0
Interface Program Data
SDATAN1 22
Memory Memory 3 AUDATA3, XMT958
RAM Input
Buffer STC
CLKIN 30
PLL
CLKSEL Clock Manager
31
32 33 34 35 24 13 2 23 12 1
IC306: AK4628VQ
192kHz 24Bit 8-channel CODEC
Audio
LIN 31 ADC HPF I/F
RIN 32 ADC HPF
LOUT1 LPF DAC DATT MCLK MCLK
27 39
LRCK 5 LRCK
ROUT1 28 LPF DAC DATT BICK 4 BICK
10 DAUX
LOUT2 25 LPF DAC DATT
Format
Converter
ROUT2 26 LPF DAC DATT
SDOUT
LOUT3 LPF DAC DATT 1 SDOS
23
9 SDTO
ROUT3 24 LPF DAC DATT SDIN1 6 SDTI1
SDIN2 7 SDTI2
SDIN3
8 SDTI3
LOUT4 21 LPF DAC DATT SDIN4 12 SDTI4
ROUT4 22 LPF DAC DATT
AK4628
SDOS 1 33 DZF2/OVF
I2C 2 32 RIN
SMUTE 3 31 LIN
BICK 4 30 NC
LRCK 5 29 MASTER
SDTI1 6 28 ROUT1
1 24 SDTI2 7 27 LOUT1
V CCB
2 23 SDTI3 8 26 ROUT2
V
CCB
3 22 SDTO 9 25 LOUT2
ENABLE
4 21 DAUX 10 24 ROUT3
B 0
5 20 DFS0 11 23 LOUT3
B 1
6 19
B 2
7 18
B
3
8 17
B 4
9 16
B
5
10 15
B 6
11 14
B 7
12 13
GND
A 2 A 3 A 4 A 5 A 6 A 7
B 2 B 3 B 4 B 5 B 6 B 7
59