Sharp FACSIMILE FO-4500 Service Manual page 98

FO-4500H
(6) Gate array (B) block
The block is composed of the gate array (B) and SRAM (2 KByte).
1) LR38292(IC16) -- pin-160, QFP (gate array B)
The device has the following functions.
1
Printing data process
The image data of the page memory for printing is converted into
400 dpi, and the smoothing and contracting processes are applied.
2
Printer (PCU) interface
The control of resetting and so on to PCU and the image data 1
processed in Item above are synchronized with the signal
(HSYNC) from PCU and are transmitted to PCU in the serial
mode.
3
DMA controller
(a) The binary-coded data of the draft transmitted in the serial
mode from the gate array (A) LZ9FJ37A(IC15) and read with
the scanner are transmitted to the page memory.
(b) The image data which will be printed are read from the page
memory, and the process
PCU in the serial mode.
4
CODEC (HD813201F) interface
(a) The timing is controlled for CPU to get an access to CODEC.
(b) The timing is controlled for CODEC to get an access to the
page memory.
5
DRAM controller
Since DRAM is used for the page memory, and the address, RAS
and CAS are controlled and refresh-controlled.
6
Panel interface
The key input detection on the operation panel, LED lighting con-
trol and LCD display control are executed.
2) LH5116NA-10 (IC19) -- pin-24, SOP (16-bit SRAM)
This SRAM is a line memory for the printing data process (resolution
power conversion, smoothening and contracting to 404 dpi) of the
gate array (B).
1
is applied to transmit the data to
LR38292 (IC16) Terminal descriptions
Pin Name
20 VCC
62 VCC
100 VCC
142 VCC
16 GND
21 GND
35 GND
48 GND
61 GND
78 GND
87 GND
101 GND
125 GND
134 GND
143 GND
MANRESB
65
66 RESETB
89 A5
90 A4
91 A3
92 A2
93 A1
70 D15
71 D14
72 D13
73 D12
74 D11
75 D10
76 D9
77 D8
79 D7
80 D6
81 D5
82 D4
83 D3
84 D2
85 D1
86 D0
88 CSB
97 RDB
98 WRB
115 SHCK0B
116 SHCK
95 GAINTB
94 CDCINTB
96 DREQ0B
99 RSTCDCB
102 CDCINT
103 BRQT
104 BACKB
105 DRQ0
106 DACK0B
107 CSCDCB
108 MDENB
109 READY
110 MAS
5 – 8
I/O Function
Power supply
Ground
O Manual reset signal
I Reset signal
I Address signal on the system side
I/O Data bus signal on the system side
I Chip select signal of gate array LR38292
Read signal on the system bus side
I
I Write signal on the system bus side
O Reversion output of clock (SHCK) from
CPU
I Clock (19.6 MHz) from CPU
O Interrupt request signal to CPU of gate
array LR38292
O Reversion output (to CPU) of interrupt
request signal from HD813201F
O Reversion output (to CPU) of DMA
transfer request signal from HD813201F
O Reset signal to HD813201F (Default:
Low)
I Interrupt request signal from HD813201F
I Bus right request signal of image bus
from HD813201F
O Bus right permission signal of image bus
to HD813201F
I DMA transfer request signal from
HD813201F
O Acknowledge signal of DMA transfer to
HD813201F
I Chip select signal to HD813201F
I Data enable signal of image bus from
HD813201F
O Ready signal of image bus access to
HD813201F
I Address strobe signal of image bus of
HD813201F