Sharp FACSIMILE FO-4500 Service Manual page 92

FO-4500H
HD6477021X20 (IC12) Terminal descriptions
Classification Code
Power Vcc
Vss
Clock EXTAL
XTAL
CK
System control RES
WDTOVF
BREQ
BACK
Operation MD2~
mode control MD0
Interrupt NMI
IRQ0~
IRQ7
IRQOUT
Address A21~A0
Data bus AD15~
AD0
DPH
DPL
Relationship between MD2 thru MD0 and operation modes
MD2 MD1 MD0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Terminal No.
I/O
(TFP-100B)
13, 38, 63, I Power
73, 80, 88
4,15,24,32, I Ground
41,50,59,70,
81,82, 92
71 I External clock
72 I Crystal
69 O System clock
76 I Reset
75 O Watch dog timer
overflow
60 I Bus right request
58 O Bus right request
acknowledge
79~77 I Mode setting
74 I No-maskable interrupt This is the interrupt request terminal which can not be masked.
65,66,67,68, I Interrupt request 0
97,98,99,100
thru 7
61 O Interrupt request
output in the slave
mode
45~42,40,39, O Address
37~33,31~25,
23~20
19~16,14, I/O Data bus
12~5,3~1
64 I/O High-order side data
bus parity
62 I/O Low-order side data
bus parity
Operation mode
MCU mode
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Name
Connect to the power supply.
Connect Vcc terminals to the power units of all systems.
If any open terminal is present, it will not operate
Connect to the ground.
Connect Vcc terminals to the power units of all systems.
If any open terminal is present, it will not operate.
Connect to the quartz oscillator. Moreover, EXTAL terminal can
input the external clock.
Use the same frequency for the quartz oscillator, external clock
and system clock.
Connect the quartz oscillator. Connect the same frequency of the
system clock (CK).
To input external clock from EXTAL terminal, open EXTAL
terminal.
Supply system clock to the peripheral device.
If this terminal is turned to the low level when NMI is at the high
level, it will be brought into the power-on state. If this terminal is
turned to the low level when NMI is at the low level, it will be
brought into the manual.reset state.
It is overflow output signal from WDT.
Select the low level to make the external device request the
release of bus right.
It indicates that the bus right is released to the external device.
When receiving BACK signal, the device which outputs BREQ
signal can know that bus right is obtained.
The terminal determines the operation mode.
During operation, don't vary any input value. The relationship
between MD2 thru MD0 and operation modes are shown in the
following list.
Either leading edge or trailing edge is selected for receiving.
This is the interrupt request terminal which can be masked.
Either level input or edge input can be selected.
It indicates that a factor of interrupt occurs.
It indicates that interrupt occurs in the bus release mode.
Address is output.
Bidirectional data bus of 16 bits
Multiplex is possible with the low-order 16 bits of the address.
Parity data corresponds to D15 thru D8.
Parity data corresponds to D7 thru D0.
IntegratedROM Bus width of area 0
8-bit size
Invalid
16-bit size
Valid —
— —
— —
— —
— —
— —
5 – 2
Function
(Continuing)