Vizio VP50HDTV10A Service Manual page 38

LVDS Transmitter:
Two LVDS channels (A and B) are available on the output of the FLI8532 to transmit data and
timing information to the display device.
The following diagram shows the available LVDS mapping for 30-bit LVDS output which is
applying to PDP panel spec:
30-bit LVDS Output Stream
To Configure for 30-bit LVDS with this data mapping:
LVDS_POWER (0x8726) = 0x3F
LVDS_DIGITAL_CTRL (0x8728) = 0bUU00UU00, where U is user options.
DISPLAY_CONTROL(0x862C)[11] = 1
For 30-bit LVDS, the following bus remappings are supported:
Swap LVDS serial stream (6:0)、(0:6) with register 0x8728[7]
Swap LVDS positive and negative differential outputs with register 0x8728[3]
Swap LVDS bus data CH0_EVEN C3_ODD and CH1_EVEN C3_EVEN with register
0x8728[2]
Note:
OSD OVL data bit is enabled with register 0x8500[9] with polarity controlled by 0x8500[10].
If 0x8500[9] = 0, then OSD OVL LVDS bit is clamped to 0.
CONFIDENTIAL – DO NOT COPY Page 7-5
File No. SG-0219