Vizio VP50HDTV10A Service Manual page 37

PORTA also includes optional signals (DIP_EXT_CLAMP, DIP_EXT_COAST,
DIP_CLEAN_HS_OUT) for interfacing to external ADC/PLL devices. These signals are not
present on PORTB. Bits 7 to 0 of PORTA can be configured as a bidirectional interface for
media card applications. Inputs to the digital input port are TTL compatible with a maximum
clock speed of 135MHz. Sync and clock polarity is programmable.
Due to pin sharing, PORTB is not available when using 48bit double wide TTL output to the
panel.
The following digital video formats are supported by FLI8532 digital video graphic port:
• ITU-BT-656
• 8-bit 4:2:2 YCbCr or YPbPr
• 16-bit 4:2:2 YCbCr or YPbPr
• 24-bit 4:4:4 YCbCr or YPbPr
• 24-bit RGB
Digital Input Port Configuration:
The Digital Input Port offers flexible mapping of the input buses for PORTA and PORTB and
allows individual Bus Flipping (MSB to LSB) for each group of 8bit inputs. The purpose of this
flexible mapping is to ease the circuit board design when interfacing to other devices. This
table below shows how the input DATA buses can be arbitrarily assigned through host
registers.
Figure 8-4 Digital Input DATA bus assignment
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